Datasheet

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STM32F405xx, STM32F407xx Electrical characteristics
Figure 39. I
2
C bus AC waveforms and measurement circuit
1. Rs= series protection resistor.
2. Rp = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
t
h(STA)
Start condition hold time 4.0 - 0.6 -
µs
t
su(STA)
Repeated Start condition
setup time
4.7 - 0.6 -
t
su(STO)
Stop condition setup time 4.0 - 0.6 - μs
t
w(STO:STA)
Stop to Start condition time
(bus free)
4.7 - 1.3 - μs
C
b
Capacitive load for each bus
line
- 400 - 400 pF
1.
Guaranteed by design, not tested in production.
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I
2
C frequencies. It must be at least 4 MHz to
achieve fast mode I
2
C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I
2
C fast mode
clock.
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
Table 53. I
2
C characteristics (continued)
Symbol Parameter
Standard mode I
2
C
(1)
Fast mode I
2
C
(1)(2)
Unit
Min Max Min Max
ai14979c
START
SDA
R
P
I²C bus
V
DD_I2C
STM32Fxx
SDA
SCL
t
f(SDA)
t
r(SDA)
SCL
t
h(STA)
t
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
r(SCL)
t
f(SCL)
t
h(SDA)
S T AR T REPEATED
START
t
su(STA)
t
su(STO)
STOP
t
w(STO:STA)
V
DD_I2C
R
P
R
S
R
S