Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
116/185 DocID022152 Rev 4
5.3.19 Communications interfaces
I
2
C interface characteristics
The STM32F405xx and STM32F407xx
I
2
C interface meets the requirements of the
standard I
2
C communication protocol with the following restrictions: the I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port
characteristics
for more details on the input/output alternate function characteristics (SDA
and SCL)
.
Table 52. Characteristics of TIMx connected to the APB2 domain
(1)
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
Symbol Parameter Conditions Min Max Unit
t
res(TIM)
Timer resolution time
AHB/APB2
prescaler distinct
from 1, f
TIMxCLK
=
168 MHz
1-t
TIMxCLK
5.95 - ns
AHB/APB2
prescaler = 1,
f
TIMxCLK
= 84 MHz
1-t
TIMxCLK
11.9 - ns
f
EXT
Timer external clock
frequency on CH1 to
CH4
f
TIMxCLK
=
168 MHz
APB2 = 84 MHz
0f
TIMxCLK
/2 MHz
084MHz
Res
TIM
Timer resolution - 16 bit
t
COUNTER
16-bit counter clock
period when internal
clock is selected
1 65536 t
TIMxCLK
t
MAX_COUNT
Maximum possible count - 32768 t
TIMxCLK
Table 53. I
2
C characteristics
Symbol Parameter
Standard mode I
2
C
(1)
Fast mode I
2
C
(1)(2)
Unit
Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 - 1.3 -
µs
t
w(SCLH)
SCL clock high time 4.0 - 0.6 -
t
su(SDA)
SDA setup time 250 - 100 -
ns
t
h(SDA)
SDA data hold time 0
(3)
-0900
(4)
t
r(SDA)
t
r(SCL)
SDA and SCL rise time - 1000 20 + 0.1C
b
300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time - 300 - 300