Datasheet

Electrical characteristics STM32F405xx, STM32F407xx
102/185 DocID022152 Rev 4
5.3.11 PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 43: EMI characteristics). It is available only on the main PLL.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
f
PLL_IN
and f
Mod
must be expressed in Hz.
As an example:
If f
PLL_IN
= 1 MHz, and f
MOD
= 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
Jitter
(3)
Master I
2
S clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
RMS - 90 -
peak
to
peak
- ±280 - ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90 -ps
WS I
2
S clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-400 - ps
I
DD(PLLI2S)
(4)
PLLI2S power consumption on
V
DD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
I
DDA(PLLI2S)
(4)
PLLI2S power consumption on
V
DDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Based on characterization, not tested in production.
Table 36. PLLI2S (audio PLL) characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 37. SSCG parameters constraint
Symbol Parameter Min Typ Max
(1)
Unit
f
Mod
Modulation frequency - - 10 KHz
md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - 2
15
−1-
1. Guaranteed by design, not tested in production.
MODEPER round f
PLL_IN
4f
Mod
×()⁄[]=
MODEPER round 10
6
410
3
×()⁄[]250==