Datasheet

Electrical characteristics STM32F37xxx
98/131 DocID022691 Rev 4
6.3.17 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 60 are preliminary values derived
from tests performed under ambient temperature, f
PCLK2
frequency and V
DDA
supply
voltage conditions summarized in Table 22.
Note: It is recommended to perform a calibration after each power-up.
Table 60. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
DDA
Power supply 2.4 - 3.6 V
V
REF+
Positive reference voltage 2.4 - V
DDA
V
I
DDA(ADC)
(1)
Current consumption from V
DDA
V
DD
= V
DDA
= 3.3 V - 0.9 - mA
I
VREF
Current on the V
REF
input pin - 160
(2)
220
(2)
µA
f
ADC
ADC clock frequency 0.6 - 14 MHz
f
S
(3)
Sampling rate 0.05 - 1 MHz
f
TRIG
(3)
External trigger frequency
f
ADC
= 14 MHz - - 823 kHz
--171/f
ADC
V
AIN
Conversion voltage range
0 (V
SSA
or V
REF-
tied to ground)
-V
REF+
V
R
SRC
(3)
Signal source impedance
See Equation 1 and
Tabl e 61 for details
--50κΩ
R
ADC
(3)
Sampling switch resistance - - 1 κΩ
C
ADC
(3)
Internal sample and hold
capacitor
--8pF
t
CAL
(3)
Calibration time
f
ADC
= 14 MHz 5.9 µs
83 1/f
ADC
t
lat
(3)
Injection trigger conversion
latency
f
ADC
= 14 MHz - - 0.214 µs
--2
(4)
1/f
ADC
t
latr
(3)
Regular trigger conversion
latency
f
ADC
= 14 MHz - - 0.143 µs
--2
(4)
1/f
ADC
t
S
(3)
Sampling time
f
ADC
= 14 MHz 0.107 - 17.1 µs
1.5 - 239.5 1/f
ADC
t
STAB
(3)
Power-up time 0 0 1 µs
t
CONV
(3)
Total conversion time (including
sampling time)
f
ADC
= 14 MHz 1 - 18 µs
14 to 252 (t
S
for sampling +12.5 for
successive approximation)
1/f
ADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I
DDA
and 60 µA
on I
DD
is present
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
4. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in Table 60