Datasheet

Electrical characteristics STM32F37xxx
96/131 DocID022691 Rev 4
Table 59. I
2
S characteristics
Symbol Parameter Conditions Min Max Unit
DuCy(SCK)
(1)
I2S slave input clock duty
cycle
Slave mode 30 70 %
f
CK
(1)
1/t
c(CK)
I
2
S clock frequency
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
1.528 1.539
MHz
Slave mode 0 12.288
t
r(CK)
(1)
t
f(CK)
I
2
S clock rise and fall time Capacitive load C
L
=30pF - 8
ns
t
v(WS)
(1)
WS valid time Master mode 4 -
t
h(WS)
(1)
WS hold time Master mode 4 -
t
su(WS)
(1)
WS setup time Slave mode 2 -
t
h(WS)
(1)
WS hold time Slave mode - -
t
w(CKH)
(1)
I2S clock high time
Master f
PCLK
= 16 MHz, audio
frequency = 48 kHz
306 -
t
w(CKL)
(1)
I2S clock low time 312 -
t
su(SD_MR)
(1)
Data input setup time
Master receiver 6 -
t
su(SD_SR)
(1)
Slave receiver 3 -
t
h(SD_MR)
(1)
Data input hold time
Master receiver 1.5 -
t
h(SD_SR)
(1)
Slave receiver 1.5 -
t
v(SD_ST)
(1)
Data output valid time
Slave transmitter
(after enable edge)
-16
t
h(SD_ST)
(1)
Data output hold time
Slave transmitter
(after enable edge)
16 -
t
v(SD_MT)
(1)
Data output valid time
Master transmitter
(after enable edge)
-2
t
h(SD_MT)
(1)
Data output hold time
Master transmitter
(after enable edge)
0-
1. Data based on design simulation, not tested in production.