Datasheet

DocID022691 Rev 4 95/131
STM32F37xxx Electrical characteristics
114
Figure 26. SPI timing diagram - master mode
(1)
1. Measurement points are done at 0.5V
DD
level and with external C
L
= 30 pF
.
ai14136V2
SCK Output
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
MSBIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)