Datasheet

Functional overview STM32F313xx
22/58 Doc ID 023636 Rev 1
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU
clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
Refer to Ta bl e 7 for the features available in I2C1 and I2C2.
3.19 Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32F313xx devices have three embedded universal synchronous/asynchronous
receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode and have LIN Master/Slave capability. The USART interfaces can be
served by the DMA controller.
Table 6. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of
suppressed spikes
 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Disabled when Wakeup from Stop
mode is enabled
Table 7. STM32F31x I
2
C implementation
I2C features
(1)
1. X = supported.
I2C1 I2C2
7-bit addressing mode X X
10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X
Independent clock X X
SMBus X X
Wakeup from STOP X X