Datasheet
Functional overview STM32F313xx
12/58 Doc ID 023636 Rev 1
level must be always greater or equal to the V
DD
voltage level and must be provided
first.
● V
BAT
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V
DD
is not present.
3.7.2 Power supply supervision
The device power on reset is controlled through the external NPOR pin. The device remains
in reset state when NPOR pin is held low.
To guarantee a proper power-on reset, the NPOR pin must be held low until V
DD
is stable.
When V
DD
is stable, the reset state can be exited by:
● either putting the NPOR pin in high impedance. NPOR pin has an internal pull up.
● or forcing the pin to high level by connecting it to V
DDA
.
3.7.3 Low-power modes
The STM32F313xx supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the RTC alarm, COMPx, I2Cx or U(S)ARTx.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
mode.
3.8 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.