Datasheet

STM32F313xx Functional overview
Doc ID 023636 Rev 1 11/58
3.3 Embedded Flash memory
All STM32F313xx devices feature up to 256 Kbytes of embedded Flash memory available
for storing programs and data. The Flash memory access time is adjusted to the CPU clock
frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states
above).
3.4 Embedded SRAM
STM32F313xx devices feature up to 48 Kbytes of embedded SRAM with hardware parity
check. The memory can be accessed in read/write at CPU clock speed with 0 wait states,
allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from CCM,
core coupled memory).
● 8 Kbytes of SRAM mapped on the instruction bus (Core Coupled Memory (CCM)),
used to execute critical routines or to access data (parity check on all of CCM RAM).
● 40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM)
3.5 Boot modes
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
● Boot from user Flash
● Boot from system memory
● Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 or USART2.
3.6 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
3.7 Power management
3.7.1 Power supply schemes
● V
SS
, V
DD
=
1.8 V+/- 8% : external power supply for I/Os and core. It is provided
externally through V
DD
pins.
● V
SSA
, V
DDA
= 1.65 to 3.6 V: external analog power supply for ADC, DACs, comparators
operational amplifiers, reset blocks, RCs and PLL (minimum voltage to be applied to
V
DDA
is 2.4 V when the DACs and operational amplifiers are used). The V
DDA
voltage