Datasheet

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STM32F303xB STM32F303xC Electrical characteristics
118
Figure 27. SPI timing diagram - master mode
(1)
1. Measurement points are done at 0.5V
DD
and with external C
L
= 30 pF.
ai14136V2
SCK Output
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
MSBIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)
Table 62. I
2
S characteristics
(1)
Symbol Parameter Conditions Min Max Unit
f
CK
1/t
c(CK)
I
2
S clock frequency
Master data: 16 bits,
audio freq=48 kHz
1.496 1.503
MHz
Slave 0 12.288
t
r(CK)
t
f(CK)
I
2
S clock rise and fall
time
Capacitive load
C
L
=30pF
-8
ns
t
w(CKH)
I
2
S clock high time Master f
PCLK
= 36 MHz,
audio frequency =
48 kHz
331 -
t
w(CKL)
I
2
S clock low time 332 -
t
v(WS)
WS valid time Master mode 4 -
t
h(WS)
WS hold time Master mode 4 -
t
su(WS)
WS setup time Slave mode 4 -
t
h(WS)
WS hold time Slave mode 0 -
Duty Cycle
I
2
S slave input clock
duty cycle
Slave mode 30 70 %