Datasheet

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STM32F303xB STM32F303xC Electrical characteristics
118
6.3.14 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under the conditions summarized in Table 22. All I/Os are CMOS and TTL
compliant.
Table 52. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Low level input
voltage
TC and TTa I/O - - 0.3 V
DD
+0.07
(1)
V
FT and FTf I/O - - 0.475 V
DD
-0.2
(1)
BOOT0 - - 0.3 V
DD
–0.3
(1)
All I/Os except BOOT0 - - 0.3 V
DD
(2)
V
IH
High level input
voltage
TC and TTa I/O 0.445 V
DD
+0.398
(1)
--
FT and FTf I/O 0.5 V
DD
+0.2
(1)
--
BOOT0 0.2 V
DD
+0.95
(1)
--
All I/Os except BOOT0 0.7 V
DD
(2)
--
V
hys
Schmitt trigger
hysteresis
TC and TTa I/O - 200
(1)
-
mVFT and FTf I/O - 100
(1)
-
BOOT0 - 300
(1)
-
I
lkg
Input leakage
current
(3)
TC, FT and FTf I/O
TTa I/O in digital mode
V
SS
 V
IN
 V
DD
--±0.1
µA
TTa I/O in digital mode
V
DD
 V
IN
 V
DDA
--1
TTa I/O in analog mode
V
SS
 V
IN
 V
DDA
--±0.2
FT and FTf I/O
(4)
V
DD
 V
IN
 5V
--10
R
PU
Weak pull-up
equivalent resistor
(5)
V
IN
V
SS
25 40 55 k
R
PD
Weak pull-down
equivalent resistor
(5)
V
IN
V
DD
25 40 55 k
C
IO
I/O pin capacitance - 5 - pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 51: I/O
current injection susceptibility.
4. To sustain a voltage higher than V
DD
+0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).