Datasheet

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STM32F303xB STM32F303xC Pinouts and pin description
53
92 58 42 PB6 I/O FTf
I2C1_SCL, USART1_TX,
TIM16_CH1N, TIM4_CH1,
TIM8_CH1, TSC_G5_IO3,
TIM8_ETR, TIM8_BKIN2,
EVENTOUT
93 59 43 PB7 I/O FTf
I2C1_SDA, USART1_RX,
TIM3_CH4, TIM4_CH2,
TIM17_CH1N, TIM8_BKIN,
TSC_G5_IO4, EVENTOUT
94 60 44 BOOT0 I B Boot memory selection
95 61 45 PB8 I/O FTf
I2C1_SCL, CAN_RX,
TIM16_CH1, TIM4_CH3,
TIM8_CH2, TIM1_BKIN,
TSC_SYNC, COMP1_OUT,
EVENTOUT
96 62 46 PB9 I/O FTf
I2C1_SDA, CAN_TX,
TIM17_CH1, TIM4_CH4,
TIM8_CH3, IR_OUT,
COMP2_OUT, EVENTOUT
97 PE0 I/O FT
(1)
USART1_TX, TIM4_ETR,
TIM16_CH1, EVENTOUT
98 PE1 I/O FT
(1)
USART1_RX, TIM17_CH1,
EVENTOUT
99 63 47 VSS_1 S Ground
100 64 48 VDD_1 S Digital power supply
1. Function availability depends on the chosen device.
When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must
not be configured in analog mode.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the RM0316 reference manual.
3. The VREF+ functionality is available only on the 100 pin package. On the 64-pin and 48-pin packages, the VREF+ is
internally connected to VDDA.
Table 11. STM32F303xB/STM32F303xC pin definitions (continued)
Pin number
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP100
LQFP64 LQFP48
Alternate functions Additional functions