Datasheet

Electrical characteristics STM32F303xB STM32F303xC
112/133 DocID023353 Rev 7
I
DDA
(3)
DAC DC current
consumption in quiescent
mode (Standby mode)
(2)
- - 380 µA
With no load, middle code (0x800) on
the input
- - 480 µA
With no load, worst code (0xF1C) on
the input
DNL
(3)
Differential non linearity
Difference between two
consecutive code-1LSB)
- - ±0.5 LSB Given for a 10-bit input code
- - ±2 LSB Given for a 12-bit input code
INL
(3)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
- - ±1 LSB Given for a 10-bit input code
- - ±4 LSB Given for a 12-bit input code
Offset
(3)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
V
DDA
/2)
-- ±10mV
-- ±3LSB
Given for a 10-bit input code at V
REF+
= 3.6 V
-- ±12LSB
Given for a 12-bit input code at V
REF+
= 3.6 V
Gain
error
(3)
Gain error - - ±0.5 % Given for a 12-bit input code
t
SETTLING
(3)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
-3 4 µsC
LOAD
 50 pF, R
LOAD
 5 k
Update
rate
(3)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-- 1 MS/sC
LOAD
 50 pF, R
LOAD
 5 k
t
WAKEUP
(3)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
-6.5 10 µs
C
LOAD
 50 pF, R
LOAD
 5 k
input code between lowest and
highest possible ones.
PSRR+
(1)
Power supply rejection ratio
(to V
DDA
) (static DC
measurement
- –67 –40 dB No R
LOAD
, C
LOAD
= 50 pF
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is
involved.
3. Data based on characterization results, not tested in production.
Table 70. DAC characteristics (continued)
Symbol Parameter Min Typ Max Unit Comments