Datasheet

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This is information on a product in full production.

November 2013 DocID023353 Rev 7 1/133

STM32F303xB STM32F303xC

ARM Cortex-M4 32b MCU+FPU, up to 256KB Flash+48KB SRAM

4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V operation

Datasheet - production data

Features

 Core: ARM

Cortex™-M4 32-bit CPU with

FPU (72 MHz max), single-cycle multiplication

and HW division, 90 DMIPS (from CCM)

/1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory access,

DSP instruction and MPU (memory protection

unit)

 Operating conditions:

–V

, V

DDA

voltage range: 2.0 V to 3.6 V

 Memories

– 128 to 256 Kbytes of Flash memory

– Up to 40 Kbytes of SRAM, with HW parity

check implemented on the first 16 Kbytes.

– Routine booster: 8 Kbytes of SRAM on

instruction and data bus, with HW parity

check (CCM)

 CRC calculation unit

 Reset and supply management

– Power-on/Power-down reset (POR/PDR)

– Programmable voltage detector (PVD)

– Low power modes: Sleep, Stop and Standby

–V

BAT

supply for RTC and backup registers

 Clock management

–4

to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC with x 16 PLL option

– Internal 40 kHz oscillator

 Up to 87 fast I/Os

– All mappable on external interrupt vectors

– Several 5 V-tolerant

 12-channel DMA controller

 Four ADCs 0.20 µS (up to 39 channels) with

selectable resolution of 12/10/8/6 bits, 0 to

3.6 V conversion range, separate analog

supply from 2 to 3.6 V

 Two 12-bit DAC channels with analog supply

from 2.4 to 3.6 V

 Seven fast rail-to-rail analog comparators with

analog supply from 2 to 3.6 V

 Four operational amplifiers that can be used in

PGA mode, all terminals accessible with analog

supply from 2.4 to 3.6 V



Up to 24 capacitive sensing channels supporting

touchkey, linear and rotary touch sensor

 Up to 13 timers

– One 32-bit timer and two 16-bit timers with

up to 4 IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– Two 16-bit 6-channel advanced-control

timers, with up to 6 PWM channels,

deadtime generation and emergency stop

– One 16-bit timer with 2 IC/OCs, 1

OCN/PWM, deadtime generation and

emergency stop

– Two 16-bit timers with IC/OC/OCN/PWM,

deadtime generation and emergency stop

– Two watchdog timers (independent, window)

– SysTick timer: 24-bit downcounter

– Two 16-bit basic timers to drive the DAC

 Calendar RTC with Alarm, periodic wakeup

from Stop/Standby

 Communication interfaces

– CAN interface (2.0B Active)

–Two I

C Fast mode plus (1 Mbit/s) with

20 mA current sink, SMBus/PMBus, wakeup

from STOP

– Up to five USART/UARTs (ISO 7816

interface, LIN, IrDA, modem control)

– Up to three SPIs, two with multiplexed

half/full duplex I2S interface, 4 to 16

programmable bit frames

– USB 2.0 full speed interface

– Infrared transmitter

 Serial wire debug, Cortex-M4 with FPU ETM,

JTAG

 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F303xB

STM32F303xC

STM32F303CB, STM32F303CC, STM32F303RB,

STM32F303RC, STM32F303VB, STM32F303VC

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP48 (7 × 7 mm)

www.st.com

Summary of content (133 pages)

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STM32F303xB STM32F303xC ARM Cortex-M4 32b MCU+FPU, up to 256KB Flash+48KB SRAM 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V operation Datasheet - production data Features  Core: ARM® Cortex™-M4 32-bit CPU with FPU (72 MHz max), single-cycle multiplication and HW division, 90 DMIPS (from CCM) /1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access, DSP instruction and MPU (memory protection unit)  Operating conditions: – VDD, VDDA voltage range: 2.0 V to 3.
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Contents STM32F303xB STM32F303xC Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 ARM® Cortex™-M4 core with FPU with embedded Flash and SRAM . . . 12 3.2 Memory protection unit (MPU) . . . . . . . . . . . .
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STM32F303xB STM32F303xC Contents 3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.18 Inter-integrated circuit interface (I2C) . . . . . . .
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Contents 7 STM32F303xB STM32F303xC 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.10 Memory characteristics . . . . . . . . . . . . . . .
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STM32F303xB STM32F303xC List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 6/133 STM32F303xB STM32F303xC EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F303xB STM32F303xC List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40.
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Introduction 1 STM32F303xB STM32F303xC Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F303xB/STM32F303xC microcontrollers. This STM32F303xB/STM32F303xC datasheet should be read in conjunction with the RM0316 STM32F303x, STM32F358xC and STM32F328x4/6/8 reference manual. The reference manual is available from the STMicroelectronics website www.st.com.
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STM32F303xB STM32F303xC 2 Description Description The STM32F303xB/STM32F303xC family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core with FPU operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM).
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Description STM32F303xB STM32F303xC Table 2.
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STM32F303xB STM32F303xC Description Figure 1. STM32F303xB/STM32F303xC block diagram TPIU ETM SWJTAG Trace/Trig OBL Ibus Cortex M4 CPU Flash interface Voltage reg. 3.3 V to 1.8V MPU/FPU Fmax: 72 MHz System NVIC CCM RAM 8KB POR Supply Supervision Reset Int. POR /PDR NRESET VDDA VSSA PVD SRAM 40 KB @VDDA @VDDA GP DMA1 7 channels RC HS 8MHz GP DMA2 5 channels PLL @VDDIO RC LS XTAL OSC 4 -32 MHz Ind. WDG32K Standby interface AHBPCLK Temp.
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Functional overview STM32F303xB STM32F303xC 3 Functional overview 3.1 ARM® Cortex™-M4 core with FPU with embedded Flash and SRAM The ARM Cortex-M4 processor with FPU is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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STM32F303xB STM32F303xC 3.4 Functional overview Embedded SRAM STM32F303xB/STM32F303xC devices feature up to 48 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from the CCM (Core Coupled Memory) RAM).  8 Kbytes of CCM RAM mapped on both instruction and data bus, used to execute critical routines or to access data (parity check on all of CCM RAM).
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Functional overview 3.7 Power management 3.7.1 Power supply schemes 3.7.2 STM32F303xB STM32F303xC  VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is provided externally through VDD pins.  VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators operational amplifiers, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the DACs and operational amplifiers are used).
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STM32F303xB STM32F303xC 3.7.4 Functional overview Low-power modes The STM32F303xB/STM32F303xC supports three low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:  Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.  Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers.
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Functional overview 3.8 STM32F303xB STM32F303xC Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled.
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STM32F303xB STM32F303xC Functional overview Figure 2. Clock tree FLITFCLK to Flash programming interface HSI to I2Cx (x = 1,2) SYSCLK I2SSRC SYSCLK to I2Sx (x = 2,3) Ext. clock I2S_CKIN USB prescaler /1,1.5 8 MHz HSI HSI RC USBCLK to USB interface /2 HCLK PLLSRC PLLMUL PLL x2,x3,.. x16 SW HSI PLLCLK HSE /8 AHB AHB prescaler /1,2,..512 APB1 prescaler /1,2,4,8,16 SYSCLK OSC_OUT OSC_IN OSC32_IN OSC32_OUT PCLK1 SYSCLK HSI LSE 4-32 MHz HSE OSC /32 LSE OSC 32.
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Functional overview 3.9 STM32F303xB STM32F303xC General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.
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STM32F303xB STM32F303xC 3.12 Functional overview Fast analog-to-digital converter (ADC) Four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F303xB/STM32F303xC family devices. The ADCs have up to 39 external channels . Some of the external channels are shared between ADC1&2 and between ADC3&4. The ADCs can perform conversions in single-shot or scan modes.
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Functional overview 3.12.3 STM32F303xB STM32F303xC VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage. 3.12.
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STM32F303xB STM32F303xC 3.15 Functional overview Fast comparators (COMP) The STM32F303xB/STM32F303xC devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity. The reference voltage can be one of the following:  External I/O  DAC output pin  Internal reference voltage or submultiple (1/4, 1/2, 3/4).
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Functional overview 3.16.1 STM32F303xB STM32F303xC Advanced timers (TIM1, TIM8) The advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers.
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STM32F303xB STM32F303xC 3.16.4 Functional overview Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management.
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Functional overview STM32F303xB STM32F303xC The RTC is an independent BCD timer/counter. It supports the following features:  Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.  Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.  Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.
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STM32F303xB STM32F303xC Functional overview ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match. The I2C interfaces can be served by the DMA controller. Refer to Table 5 for the features available in I2C1 and I2C2. Table 5.
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Functional overview 3.20 STM32F303xB STM32F303xC Universal asynchronous receiver transmitter (UART) The STM32F303xB/STM32F303xC devices have 2 embedded universal asynchronous receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC, multiprocessor communication mode and single-wire half-duplex communication mode. The UART4 interface can be served by the DMA controller. Refer to Table 6 for the features available in all U(S)ART interfaces. Table 6.
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STM32F303xB STM32F303xC 3.21 Functional overview Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.
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Functional overview 3.24 STM32F303xB STM32F303xC Infrared Transmitter The STM32F303xB/STM32F303xC devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below. TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.
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STM32F303xB STM32F303xC Functional overview Table 8.
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Functional overview STM32F303xB STM32F303xC 3.26 Development support 3.26.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.26.
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STM32F303xB STM32F303xC Pinouts and pin description VDD_1 VSS_1 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 4.
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Pinouts and pin description STM32F303xB STM32F303xC VDD_1 VSS_1 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 5.
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STM32F303xB STM32F303xC Pinouts and pin description 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_1 VSS_1 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 6.
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Pinouts and pin description STM32F303xB STM32F303xC Table 10. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Pin functions 34/133 Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.
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STM32F303xB STM32F303xC Pinouts and pin description Table 11.
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Pinouts and pin description STM32F303xB STM32F303xC Table 11.
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STM32F303xB STM32F303xC Pinouts and pin description Table 11.
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Pinouts and pin description STM32F303xB STM32F303xC Table 11.
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STM32F303xB STM32F303xC Pinouts and pin description Table 11.
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Pinouts and pin description STM32F303xB STM32F303xC Table 11.
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STM32F303xB STM32F303xC Pinouts and pin description Table 11.
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Port & Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 TIM8_ ETR AF11 AF12 AF14 AF15 TIM2_ CH1_ ETR TSC_ G1_IO1 USART2 COMP1 TIM8_ _CTS _OUT BKIN TIM2_ CH2 TSC_ G1_IO2 USART2 _RTS TIM15_ CH1N EVENT OUT PA2 TIM2_ CH3 TSC_ G1_IO3 USART2 COMP2 TIM15_ _TX _OUT CH1 EVENT OUT PA3 TIM2_ CH4 TSC_ G1_IO4 USART2 _RX EVENT OUT PA0 PA1 RTC_ REFIN DocID023353 Rev 7 PA4 TIM3_ TSC_ CH2 G2_IO1 SPI1_ NSS TSC_ G2_IO2 SPI1_ SCK SPI3_NSS, I2S3_WS EVENT OUT TIM15_ CH2 USART2
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Port & Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 PA12 TIM16_ CH1 PA13 SWDIO TIM16_ -JTMS CH1N TSC_ G4_IO3 IR_ OUT USART3 _CTS PA14 SWCLK -JTCK TSC_ I2C1_ G4_IO4 SDA TIM8_ TIM1_BKIN CH2 USART2 _TX SPI1_ NSS USART2 _RX PA15 JTDI TIM2_ CH1_ ETR TIM1_CH2N TIM8_ CH1 I2C1_ SCL SPI3_NSS, I2S3_WS AF8 AF9 AF10 USART1 COMP2 TIM4_ CAN_TX _RTS _OUT CH2 TIM4_ CH3 AF11 TIM1_ETR AF12 AF14 USB_ DP AF15 EVENT OUT EVENT OUT EVENT OUT TIM1_ BKIN STM32F303xB STM32F303xC Table 12.
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Port & Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 PB0 TIM3_ CH3 TSC_ G3_IO2 TIM8_ CH2N TIM1_CH2N PB1 TIM3_ CH4 TSC_ G3_IO3 TIM8_ CH3N TIM1_CH3N AF7 AF8 AF9 AF10 AF12 EVENT OUT COMP4_ OUT EVENT OUT TSC_ G3_IO4 PB2 DocID023353 Rev 7 PB3 JTDOTIM2_ TRACES CH2 WO PB4 NJTRST AF15 EVENT OUT TSC_ G5_IO1 TIM8_ CH1N SPI1_ SCK SPI3_SCK, I2S3_CK USART2_ TX TIM3_ ETR EVENT OUT TIM16_ TIM3_ CH1 CH1 TSC_ G5_IO2 TIM8_ CH2N SPI1_ MISO SPI3_MISO, I2S3ext_SD USART2_ RX TIM17_ BKIN EVE
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Port & Pin Name AF0 AF1 AF2 PB13 TIM15_ CH1 PB14 PB15 RTC_ REFIN TIM15_ TIM15_ CH2 CH1N AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 TSC_ G6_IO3 SPI2_SCK, I2S2_CK TIM1_ CH1N USART3_ CTS EVENT OUT TSC_ G6_IO4 SPI2_MISO, TIM1_ I2S2ext_SD CH2N USART3_ RTS EVENT OUT TIM1_ CH3N SPI2_MOSI, I2S2_SD EVENT OUT STM32F303xB STM32F303xC Table 13.
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Port & Pin Name AF1 AF2 AF3 AF4 AF5 AF6 AF7 DocID023353 Rev 7 PC0 EVENTOUT PC1 EVENTOUT PC2 EVENTOUT PC3 EVENTOUT PC4 EVENTOUT PC5 EVENTOUT PC6 EVENTOUT TIM3_CH1 TIM8_CH1 I2S2_MCK COMP6_OUT PC7 EVENTOUT TIM3_CH2 TIM8_CH2 I2S3_MCK COMP5_OUT PC8 EVENTOUT TIM3_CH3 TIM8_CH3 PC9 EVENTOUT TIM3_CH4 TIM8_CH4 I2S_CKIN TIM8_BKIN2 PC10 EVENTOUT TIM8_CH1N UART4_TX SPI3_SCK, I2S3_CK USART3_TX PC11 EVENTOUT TIM8_CH2N UART4_RX SPI3_MISO, I2S3ext_SD USART3_RX PC12 EVE
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Port & Pin Name AF1 AF2 AF3 AF4 AF5 AF6 AF7 DocID023353 Rev 7 PD0 EVENTOUT CAN_RX PD1 EVENTOUT PD2 EVENTOUT TIM3_ETR PD3 EVENTOUT TIM2_CH1_ETR USART2_CTS PD4 EVENTOUT TIM2_CH2 USART2_RTS PD5 EVENTOUT PD6 EVENTOUT TIM2_CH4 USART2_RX PD7 EVENTOUT TIM2_CH3 USART2_CK PD8 EVENTOUT USART3_TX PD9 EVENTOUT USART3_RX PD10 EVENTOUT USART3_CK PD11 EVENTOUT USART3_CTS PD12 EVENTOUT TIM4_CH1 TSC_G8_IO1 PD13 EVENTOUT TIM4_CH2 TSC_G8_IO2 PD14 EVENTOUT TIM4_CH3 TSC_
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Port & Pin Name AF0 AF1 PE0 EVENTOUT PE1 EVENTOUT AF2 AF3 TIM4_ETR PE2 TRACECK EVENTOUT TIM3_CH1 TSC_G7_IO1 PE3 TRACED0 EVENTOUT TIM3_CH2 TSC_G7_IO2 PE4 TRACED1 EVENTOUT TIM3_CH3 TSC_G7_IO3 PE5 TRACED2 EVENTOUT TIM3_CH4 TSC_G7_IO4 PE6 TRACED3 EVENTOUT DocID023353 Rev 7 EVENTOUT TIM1_ETR PE8 EVENTOUT TIM1_CH1N PE9 EVENTOUT TIM1_CH1 PE10 EVENTOUT TIM1_CH2N PE11 EVENTOUT TIM1_CH2 PE12 EVENTOUT TIM1_CH3N PE13 EVENTOUT TIM1_CH3 PE14 EVENTOUT TIM1_CH4 PE15
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Port & Pin Name AF1 AF2 AF3 AF4 PF0 I2C2_SDA PF1 I2C2_SCL AF5 AF6 AF7 TIM1_CH3N PF2 EVENTOUT PF4 EVENTOUT COMP1_OUT PF6 EVENTOUT TIM4_CH4 PF9 EVENTOUT TIM15_CH1 SPI2_SCK PF10 EVENTOUT TIM15_CH2 SPI2_SCK I2C2_SCL USART3_RTS STM32F303xB STM32F303xC Table 17.
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Memory mapping 5 STM32F303xB STM32F303xC Memory mapping Figure 7.
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STM32F303xB STM32F303xC Memory mapping Table 18.
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Memory mapping STM32F303xB STM32F303xC Table 18.
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STM32F303xB STM32F303xC Memory mapping Table 18.
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Electrical characteristics STM32F303xB STM32F303xC 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F303xB STM32F303xC 6.1.6 Electrical characteristics Power supply scheme Figure 10. Power supply scheme VBAT IN VDD 4 × VDD Level shifter OUT GP I/Os 4 × 100 nF + 1 × 4.7 μF Backup circuitry (LSE,RTC, Wake-up logic Backup registers) Po wer swi tch 1.65 - 3.6V IO Logic Kernel logic (CPU, Digital & Memories) Regulator 3 × VSS VDDA VDDA VREF 10 nF + 1 μF VREF+ 10 nF + 1 μF VREF- ADC/ DAC Analog: RCs, PLL, comparators, OPAMP, .... VSSA MS19875V3 1.
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Electrical characteristics 6.1.7 STM32F303xB STM32F303xC Current consumption measurement Figure 11.
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STM32F303xB STM32F303xC 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics, Table 20: Current characteristics, and Table 21: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 19.
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Electrical characteristics STM32F303xB STM32F303xC Table 20. Current characteristics Symbol Ratings Max.
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STM32F303xB STM32F303xC Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 22. General operating conditions Symbol Parameter fHCLK Min Max Internal AHB clock frequency 0 72 fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 72 Standard operating voltage 2 3.6 2 3.
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Electrical characteristics 6.3.2 STM32F303xB STM32F303xC Operating conditions at power-up / power-down The parameters given in Table 23 are derived from tests performed under the ambient temperature condition summarized in Table 22. Table 23. Operating conditions at power-up / power-down Symbol Parameter tVDD tVDDA 6.3.
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STM32F303xB STM32F303xC Electrical characteristics Table 25. Programmable voltage detector characteristics Symbol Min(1) Typ Max(1) Rising edge 2.1 2.18 2.26 Falling edge 2 2.08 2.16 Rising edge 2.19 2.28 2.37 Falling edge 2.09 2.18 2.27 Rising edge 2.28 2.38 2.48 Falling edge 2.18 2.28 2.38 Rising edge 2.38 2.48 2.58 Falling edge 2.28 2.38 2.48 Rising edge 2.47 2.58 2.69 Falling edge 2.37 2.48 2.59 Rising edge 2.57 2.68 2.79 Falling edge 2.47 2.58 2.
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Electrical characteristics 6.3.4 STM32F303xB STM32F303xC Embedded reference voltage The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22. Table 26.
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STM32F303xB STM32F303xC Electrical characteristics The parameters given in Table 28 to Table 32 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22. Table 28. Typical and maximum current consumption from VDD supply at VDD = 3.
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Electrical characteristics STM32F303xB STM32F303xC Table 28. Typical and maximum current consumption from VDD supply at VDD = 3.6V (continued) All peripherals enabled Symbol Parameter Conditions IDD Supply current in Sleep mode, executing from Flash or RAM External clock (HSE bypass) Internal clock (HSI) fHCLK Max @ TA(1) Typ All peripherals disabled Max @ TA(1) Typ 25 °C 85 °C 105 °C 72 MHz 44.0 48.4 49.4 50.5 64 MHz 39.2 43.3 44.0 48 MHz 29.6 32.7 32 MHz 19.
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STM32F303xB STM32F303xC Electrical characteristics Table 30. Typical and maximum VDD consumption in Stop and Standby modes Symbol Parameter IDD Typ @VDD (VDD=VDDA) Max(1) 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 °C 85 °C 105 °C Conditions Regulator in run mode, 20.05 20.33 20.42 20.50 20.67 20.80 44.2(2) 553 1202(2) Supply all oscillators OFF current in Stop mode Regulator in low-power 7.63 7.77 7.90 8.07 8.17 8.33 30.
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Electrical characteristics STM32F303xB STM32F303xC Table 32. Typical and maximum current consumption from VBAT supply Symbol Para meter Max @VBAT = 3.6 V(2) Typ @VBAT Conditions (1) LSE & RTC ON; "Xtal mode" lower driving capability; Backup LSEDRV[1: domain 0] = '00' IDD_VBAT supply LSE & RTC current ON; "Xtal mode" higher driving capability; LSEDRV[1: 0] = '11' 1.65V 1.8V 2V 0.48 0.50 0.52 2.4V 2.7V 0.58 3V Unit T = TA = TA = 3.3V 3.6V A 25°C 85°C 105°C 0.65 0.72 0.80 0.90 1.1 1.5 2.
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STM32F303xB STM32F303xC Electrical characteristics Typical current consumption The MCU is placed under the following conditions:  VDD = VDDA = 3.
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Electrical characteristics STM32F303xB STM32F303xC Table 34. Typical current consumption in Sleep mode, code running from Flash or RAM Typ Symbol IDD Parameter Conditions Supply current in Sleep mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash or RAM IDDA(1) (2) Supply current in Sleep mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 44.1 7.0 64 MHz 39.7 6.3 48 MHz 30.3 4.9 32 MHz 20.5 3.5 24 MHz 15.4 2.8 16 MHz 10.
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STM32F303xB STM32F303xC Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 52: I/O static characteristics.
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Electrical characteristics STM32F303xB STM32F303xC Table 35. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V Cext = 0 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 10 pF C = CINT + CEXT +CS ISW I/O current consumption VDD = 3.3 V Cext = 22 pF C = CINT + CEXT +CS VDD = 3.3 V Cext = 33 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 47 pF C = CINT + CEXT+ CS 1. CS = 5 pF (estimated value). 70/133 DocID023353 Rev 7 I/O toggling frequency (fSW) Typ 2 MHz 0.
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STM32F303xB STM32F303xC Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions:  all I/O pins are in analog input configuration  all peripherals are disabled unless otherwise mentioned   the given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on ambient operating temperature at 25°C and VDD = VDDA = 3.3 V. Table 36.
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Electrical characteristics STM32F303xB STM32F303xC Table 36. Peripheral current consumption (continued) Peripheral Typical consumption(1) Unit IDD TIM6 9.7 TIM7 12.1 WWDG 6.4 SPI2 40.4 SPI3 40.0 USART2 41.9 USART3 40.2 UART4 36.5 UART5 30.8 I2C1 10.5 I2C2 10.4 USB 26.2 CAN 33.4 PWR 5.7 DAC 15.4 µA/MHz 1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included.
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STM32F303xB STM32F303xC 6.3.6 Electrical characteristics Wakeup time from low-power mode The wakeup times given in Table 37 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:  For Stop or Sleep mode: the wakeup event is WFE.  WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22. Table 37.
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Electrical characteristics 6.3.7 STM32F303xB STM32F303xC External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 13. Table 38.
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STM32F303xB STM32F303xC Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 14 Table 39. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.
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Electrical characteristics STM32F303xB STM32F303xC High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 40.
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STM32F303xB STM32F303xC Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
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Electrical characteristics STM32F303xB STM32F303xC Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 41.
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STM32F303xB STM32F303xC Electrical characteristics Figure 16. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN Drive programmable amplifier 32.768 kH z resonator CL2 Note: OSC32_OU T An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
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Electrical characteristics 6.3.8 STM32F303xB STM32F303xC Internal clock source characteristics The parameters given in Table 42 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22. High-speed internal (HSI) RC oscillator Table 42.
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STM32F303xB STM32F303xC Electrical characteristics Low-speed internal (LSI) RC oscillator Table 43. LSI oscillator characteristics(1) Symbol fLSI tsu(LSI) Parameter Min Typ Max Unit 30 40 50 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.75 1.2 µA Frequency (2) IDD(LSI)(2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.
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Electrical characteristics 6.3.10 STM32F303xB STM32F303xC Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 45. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA–40 to +105 °C 40 53.
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STM32F303xB STM32F303xC 6.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32F303xB STM32F303xC Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
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STM32F303xB STM32F303xC Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance:  A supply overvoltage is applied to each power supply pin  A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 50. Electrical sensitivities Symbol LU 6.3.
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Electrical characteristics STM32F303xB STM32F303xC Table 51.
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STM32F303xB STM32F303xC 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under the conditions summarized in Table 22. All I/Os are CMOS and TTL compliant. Table 52. I/O static characteristics Symbol VIL VIH Parameter Low level input voltage High level input voltage Conditions Vhys Ilkg Input leakage current (3) Typ Max Unit (1) TC and TTa I/O - - 0.
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Electrical characteristics STM32F303xB STM32F303xC All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os. Figure 18. TC and TTa I/O input characteristics - CMOS port VIL/VIH (V) min nts VIH dard S stan CMO VIHmin 2.0 Tested eme requir = 0.7 VDD 98 ns +0.3 5V DD imulatio 0.
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STM32F303xB STM32F303xC Electrical characteristics Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port VIL/VIH (V) 2.0 Tested in 0.7 VDD production 0.2 ulations V DD+ = 0.5 sign sim e on d ased V IHmin B -0.2 tions 75V DD simula = 0.4 ign V ILmax on des d Base Area not determined 1.0 CMOS standard requirements VILmax = 0.3VDD oduction 0.5 ts VIHmin = quiremen andard re CMOS st Tested in pr VDD (V) 2.0 3.6 MS30257V2 Figure 21.
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Electrical characteristics STM32F303xB STM32F303xC Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.
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STM32F303xB STM32F303xC Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 54, respectively. Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22. Table 54.
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Electrical characteristics STM32F303xB STM32F303xC Figure 22. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON 50pF tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131c 6.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 52).
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STM32F303xB STM32F303xC Electrical characteristics Figure 23. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal Reset Filter 0.1 μF MS19878V1 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 55. Otherwise the reset will not be taken into account by the device. 6.3.
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Electrical characteristics STM32F303xB STM32F303xC Table 57. IWDG min/max timeout period at 40 kHz (LSI) (1) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz.
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STM32F303xB STM32F303xC 6.3.17 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 59. Refer also to Section 6.3.
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Electrical characteristics STM32F303xB STM32F303xC Table 60. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit 50 260 ns Pulse width of spikes that are suppressed by the analog filter tAF 1. Guaranteed by design, not tested in production. Figure 24.
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STM32F303xB STM32F303xC Electrical characteristics SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 61 for SPI or in Table 62 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22. Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 61.
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Electrical characteristics STM32F303xB STM32F303xC Figure 25. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) tSU(NSS) SCK Input CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 26.
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STM32F303xB STM32F303xC Electrical characteristics Figure 27. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INP UT tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTPUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136V2 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Table 62.
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Electrical characteristics STM32F303xB STM32F303xC Table 62.
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STM32F303xB STM32F303xC Electrical characteristics Figure 29. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) LSB transmit(2) SDtransmit MSB transmit LSB receive(2) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2.
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Electrical characteristics STM32F303xB STM32F303xC Table 64. USB DC electrical characteristics Symbol Parameter Min.(1) Max.(1) Unit 3.0(3) 3.6 V I(USB_DP, USB_DM) 0.2 - Includes VDI range 0.8 2.5 1.3 2.0 Conditions Input levels VDD USB operating voltage(2) VDI(4) Differential input sensitivity VCM(4) Differential common mode range VSE(4) Single ended receiver threshold V Output levels VOL Static output level low RL of 1.5 k to 3.6 V(5) - 0.
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STM32F303xB STM32F303xC Electrical characteristics Table 65. USB: Full-speed electrical characteristics(1) Symbol Parameter Conditions Min Typ Max Unit CL = 50 pF 4 - 20 ns CL = 50 pF 4 - 20 ns tr/tf 90 - 110 % 1.3 - 2.0 V 28 40 44  Driver characteristics tr tf trfm VCRS Rise time(2) Fall time (2) Rise/ fall time matching Output signal crossover voltage Output driver Z Impedance(3) DRV driving high and low 1. Guaranteed by design, not tested in production. 2.
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Electrical characteristics 6.3.18 STM32F303xB STM32F303xC ADC characteristics Unless otherwise specified, the parameters given in Table 66 to Table 68 are guaranteed by design, with conditions summarized in Table 22. Table 66. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage for ADC 2 - 3.6 V VREF+ Positive reference voltage 2 - VDDA V 0.14 - 72 MHz Resolution = 12 bits, Fast Channel 0.01 - 5.14 Resolution = 10 bits, Fast Channel 0.
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STM32F303xB STM32F303xC Electrical characteristics Table 66. ADC characteristics (continued) Symbol tCONV(1) Parameter Total conversion time (including sampling time) Conditions Min Typ Max Unit fADC = 72 MHz Resolution = 12 bits 0.19 - 8.52 µs 14 to 614 (tS for sampling + 12.5 for successive approximation) Resolution = 12 bits 1/fADC 1. Data guaranteed by design. 2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
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Electrical characteristics STM32F303xB STM32F303xC Table 67. Maximum ADC RAIN (1) (continued) Resolution 6 bits RAIN max (k) Sampling cycle @ 72 MHz Sampling time [ns] @ 72 MHz Fast channels(2) Slow channels Other channels(3) 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1.
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STM32F303xB STM32F303xC Electrical characteristics Table 68. ADC accuracy - limited test conditions (1)(2) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL ENOB SINAD Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Min Conditions ADC clock freq.  72 MHz Sampling freq.  5 Msps VDDA = VREF+ = 3.
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Electrical characteristics STM32F303xB STM32F303xC Table 68. ADC accuracy - limited test conditions (1)(2) (continued) Symbol Parameter Single ended SNR THD Signal-tonoise ratio Total harmonic distortion Min Conditions ADC clock freq.  72 MHz Sampling freq  5 Msps VDDA = VREF+ = 3.3 V 25°C Differential Single ended Differential Max (3) Typ Fast channel 5.1 Ms 64 67 - Slow channel 4.8 Ms 65 67 - Fast channel 5.1 Ms 68 70 - Slow channel 4.8 Ms 69 70 - Fast channel 5.
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STM32F303xB STM32F303xC Electrical characteristics Table 69. ADC accuracy (1)(2)(3) Symbol Parameter ET Single Ended Total unadjusted error Differential Single Ended EO Offset error Differential Single Ended EG ED EL ENOB Gain error Differential linearity error Integral linearity error Effective number of bits Min (4) Max(4) Fast channel 5.1 Ms - 7 Slow channel 4.8 Ms - 7 Fast channel 5.1 Ms - 7 Slow channel 4.8 Ms - 7 Fast channel 5.1 Ms - 5 Slow channel 4.
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Electrical characteristics STM32F303xB STM32F303xC Table 69. ADC accuracy (continued)(1)(2)(3) Symbol Parameter Single Ended Signal-tonoise and SINAD distortion ratio Signal-tonoise ratio SNR Differential ADC clock freq.  72 MHz, Sampling freq.  5 Msps, 2 V  VDDA, VREF+  3.6 V Single Ended Differential Single Ended Total harmonic distortion THD Min (4) Max(4) Fast channel 5.1 Ms - 63 Slow channel 4.8 Ms - 63 Fast channel 5.1 Ms - 67 Slow channel 4.8 Ms - 67 Fast channel 5.
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STM32F303xB STM32F303xC Electrical characteristics Figure 32. Typical connection diagram using the ADC VDD RAIN(1) VAIN Sample and hold ADC converter VT 0.6 V RADC AINx Cparasitic IL±1 μA VT 0.6 V 12-bit converter CADC MS19881V2 1. Refer to Table 66 for the values of RAIN. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy.
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Electrical characteristics STM32F303xB STM32F303xC Table 70. DAC characteristics (continued) Symbol Min Typ Max Unit Comments DAC DC current consumption in quiescent mode (Standby mode)(2) - - 380 µA With no load, middle code (0x800) on the input - - 480 µA With no load, worst code (0xF1C) on the input Differential non linearity Difference between two consecutive code-1LSB) - - ±0.
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STM32F303xB STM32F303xC Electrical characteristics Figure 33. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD DACx_OUT 12-bit digital to analog converter C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.20 Comparator characteristics Table 71.
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Electrical characteristics STM32F303xB STM32F303xC Table 71. Comparator characteristics(1) (continued) Symbol IDD(COMP) Vhys Parameter COMP current consumption Comparator hysteresis Conditions Min Typ Max Ultra-low power mode - 1.2 1.
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STM32F303xB STM32F303xC 6.3.21 Electrical characteristics Operational amplifier characteristics Table 72. Operational amplifier characteristics(1) Symbol Parameter VDDA Analog supply voltage CMIR Common mode input range Condition 25°C, No Load on output. VIOFFSET Input offset voltage Maximum calibration range All voltage/Temp. Min Typ Max Unit 2.4 - 3.6 V 0 - VDDA V - - 4 - - 6 mV 25°C, No Load on output. - - 1.6 All voltage/Temp.
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Electrical characteristics STM32F303xB STM32F303xC Table 72. Operational amplifier characteristics(1) (continued) Symbol PGA gain Rnetwork Parameter Condition Min Typ Max - 2 - - 4 - - 8 - - 16 - Gain=2 - 5.4/5.4 - Gain=4 - 16.2/5.4 - Gain=8 - 37.8/5.4 - Gain=16 - 40.5/2.7 - -1% - 1% - - 0.
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STM32F303xB STM32F303xC Electrical characteristics Figure 34.
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Electrical characteristics 6.3.22 STM32F303xB STM32F303xC Temperature sensor characteristics Table 73. TS characteristics Symbol Parameter TL(1) Min Typ Max Unit - 1 2 °C Average slope 4.0 4.3 4.6 mV/°C Voltage at 25 °C 1.34 1.43 1.52 V 4 - 10 µs 2.2 - - µs VSENSE linearity with temperature (1) Avg_Slope V25 tSTART(1) TS_temp(1)(2) Startup time ADC sampling time when reading the temperature 1. Guaranteed by design, not tested in production. 2.
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STM32F303xB STM32F303xC Package characteristics 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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Package characteristics STM32F303xB STM32F303xC Figure 35. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE L D A1 K ccc C L1 D1 D3 75 51 50 100 E E3 E1 b 76 26 PIN 1 1 IDENTIFICATION 25 e 1L_ME_V3 1. Drawing is not to scale. Table 76. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data Symbol Min Typ A 0.05 A2 1.35 b 0.17 c 0.09 D 15.80 D1 13.80 D3 120/133 Max Min Typ 1.
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STM32F303xB STM32F303xC Package characteristics Table 76. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data (continued) Symbol E1 inches(1) millimeters Min Typ Max Min Typ Max 13.80 14.00 14.2 0.5433 0.5512 0.5591 E3 12.00 0.4724 e 0.50 0.0197 L 0.45 0.60 L1 K 0.75 0.0177 0.0236 1.00 0° 0.0295 0.0394 3.5° 7° ccc 0° 3.5° 0.08 7° 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 36.
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Package characteristics STM32F303xB STM32F303xC Figure 37. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE A1 ccc C K L D L1 D1 D3 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 E3 b 17 16 1 e 5W_ME_V2 1. Drawing is not to scale. Table 77. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Min Typ 1.60 A1 0.05 A2 1.350 b 0.17 122/133 Max Max 0.0630 0.
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STM32F303xB STM32F303xC Package characteristics Table 77. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ 0.20 0.0035 Max c 0.09 D 11.80 12.00 12.20 0.4646 0.4724 0.4803 D1 9.80 10.00 10.20 0.3858 0.3937 0.4016 D3 0.0079 7.50 0.2953 E 11.80 12.00 12.20 0.4646 0.4724 0.4803 E1 9.80 10.00 10.20 0.3858 0.3937 0.4016 E3 7.50 0.2953 e 0.50 0.0197 L 0.45 L1 K 0.60 0.75 0.0177 0.
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Package characteristics STM32F303xB STM32F303xC Figure 39. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE ccc C K A1 D L D1 L1 D3 36 25 37 24 48 PIN 1 IDENTIFICATION E E1 E3 b 13 1 12 e 5B_ME_V2 1. Drawing is not to scale. Table 78. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 D 8.
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STM32F303xB STM32F303xC Package characteristics Table 78. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data (continued) Symbol L Min Typ Max Min Typ Max 0.45 0.60 0.75 0.0177 0.0236 0.0295 7° 0° L1 K inches(1) millimeters 1.00 0° 0.0394 3.5° ccc 3.5° 0.08 7° 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 40. LQFP48 recommended footprint 0.50 1.20 36 9.70 0.30 25 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.
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Package characteristics 7.2 STM32F303xB STM32F303xC Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 22: General operating conditions on page 59.
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STM32F303xB STM32F303xC 7.2.2 Package characteristics Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Part numbering. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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Package characteristics STM32F303xB STM32F303xC Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.
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STM32F303xB STM32F303xC 8 Part numbering Part numbering Table 80.
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Revision history 9 STM32F303xB STM32F303xC Revision history Table 81. Document revision history 130/133 Date Revision Changes 22-Jun-2012 1 Initial release 07-Sep-2012 2 Modified Features on cover page. Modified Table 2: STM32F301xx family device features and peripheral counts Added clock tree to Section 3.
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STM32F303xB STM32F303xC Revision history Table 81. Document revision history Date 05-Dec-2012 Revision Changes 4 Updated first page Removed references to VDDSDx and VSSSD Added reference to PM0214 in Section 1 Moved Temp. sensor calibartion values toTable 74 and VREF calibration values to Table 27 Updated Table 3: STM32F303xx family device features and peripheral counts UpdatedSection 3.4: Embedded SRAM Updated Section 3.2: Memory protection unit (MPU) Updated Section 3.
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Revision history STM32F303xB STM32F303xC Table 81. Document revision history Date 08-Jan-2013 24-Jun-2013 13-Nov-2013 132/133 Revision Changes 5 Updated Vhys and Ilkg in Table 52: I/O static characteristics. Updated VIL(NRST), VIH(NRST), and VNF(NRST) in Table 55: NRST pin characteristics. Updated Table 68: ADC accuracy - limited test conditions and Table 64: ADC accuracy - limited test conditions 2).
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