Datasheet

DocID17050 Rev 9 79/175
STM32F21xxx Electrical characteristics
174
Table 21. Typical and maximum current consumption in Sleep mode
Symbol Parameter Conditions f
HCLK
Typ Max
(1)
Unit
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
I
DD
Supply current in
Sleep mode
External clock
(2)
,
all peripherals enabled
(3)
120 MHz 38 51 61
mA
90 MHz 30 43 53
60 MHz 20 33 43
30 MHz 11 25 35
25 MHz 8 21 31
16 MHz 6 19 29
8 MHz 3.6 17.0 27.0
4 MHz 2.4 15.4 25.3
2 MHz 1.9 14.9 24.7
External clock
(2)
, all
peripherals disabled
120 MHz 8 21 31
90 MHz 7 20 30
60 MHz 5 18 28
30 MHz 3.5 16.0 26.0
25 MHz 2.5 16.0 25.0
16 MHz 2.1 15.1 25.0
8 MHz 1.7 15.0 25.0
4 MHz 1.5 14.6 24.6
2 MHz 1.4 14.2 24.3
1. Based on characterization, tested in production at V
DD
max and f
HCLK
max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when f
HCLK
> 25 MHz.
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is on (ADON bit is set in the ADC_CR2 register).