Datasheet

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STM32F21xxx Pinouts and pin description
174
13 22 33 39 R1 V
DDA
S
14 23 34 40 N3
PA0/WKUP
(PA0)
I/O FT
(4)(5)
USART2_CTS, UART4_TX,
ETH_MII_CRS,
TIM2_CH1_ETR,
TIM5_CH1, TIM8_ETR,
EVENTOUT
ADC123_IN0,
WKUP
15 24 35 41 N2 PA1 I/O FT
(4)
USART2_RTS, UART4_RX,
ETH_RMII_REF_CLK,
ETH_MII_RX_CLK, TIM5_CH2,
TIM2_CH2, EVENTOUT
ADC123_IN1
16 25 36 42 P2 PA2 I/O FT
(4)
USART2_TX,TIM5_CH3,
TIM9_CH1, TIM2_CH3,
ETH_MDIO, EVENTOUT
ADC123_IN2
- - - 43 F4 PH2 I/O FT ETH_MII_CRS, EVENTOUT
- - - 44 G4 PH3 I/O FT ETH_MII_COL, EVENTOUT
- - - 45 H4 PH4 I/O FT
I2C2_SCL,
OTG_HS_ULPI_NXT,
EVENTOUT
- - - 46 J4 PH5 I/O FT I2C2_SDA, EVENTOUT
17 26 37 47 R2 PA3 I/O FT
(4)
USART2_RX, TIM5_CH4,
TIM9_CH2, TIM2_CH4,
OTG_HS_ULPI_D0,
ETH_MII_COL, EVENTOUT
ADC123_IN3
18 27 38 48 - V
SS
S
L4 REGOFF I/O
19 28 39 49 K4 V
DD
S
20 29 40 50 N4 PA4 I/O TTa
(4)
SPI1_NSS, SPI3_NSS,
USART2_CK, DCMI_HSYNC,
OTG_HS_SOF, I2S3_WS,
EVENTOUT
ADC12_IN4,
DAC_OUT1
21 30 41 51 P4 PA5 I/O TTa
(4)
SPI1_SCK,
OTG_HS_ULPI_CK,
TIM2_CH1_ETR, TIM8_CH1N,
EVENTOUT
ADC12_IN5
/DAC_OUT2
Table 7. STM32F21x pin and ball definitions (continued)
Pins
Pin name
(function after
reset)
(1)
Pin type
I / O structure
Note
Alternate functions
Additional
functions
LQFP64
LQFP100 LQFP144 LQFP176
UFBGA176