Datasheet

DocID17050 Rev 9 25/175
STM32F21xxx Functional overview
174
Figure 7. Startup in regulator OFF: slow V
DD
slope
- power-down reset risen after V
CAP_1
/V
CAP_2
stabilization
1. This figure is valid both whatever the internal reset mode (ON or OFF).
Figure 8. Startup in regulator OFF: fast V
DD
slope
- power-down reset risen before V
CAP_1
/V
CAP_2
stabilization
3.16.3 Regulator ON/OFF and internal reset ON/OFF availability
V
DD
time
1.08 V
PDR=1.8 V
V
CAP_1
/V
CAP_2
1.2 V
time
PA0 tied to NRST
NRST
V
DD
time
1.08 V
PDR=1.8 V
V
CAP_1
/V
CAP_2
1.2 V
time
PA0 asserted externally
NRST
Table 3. Regulator ON/OFF and internal reset ON/OFF availability
Package
Regulator ON/internal
reset ON
Regulator ON/internal
reset OFF
Regulator
OFF/internal reset ON
LQFP64
LQFP100
LQFP144
LQFP176
Yes No No
UFBGA176
Yes
REGOFF set to V
SS
No
Yes
REGOFF set to V
DD