Datasheet

DocID17050 Rev 9 23/175
STM32F21xxx Functional overview
174
There are three power modes configured by software when the regulator is ON:
• MR is used in the nominal regulation mode
• LPR is used in Stop modes
The LP regulator mode is configured by software when entering Stop mode.
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost).
Two external ceramic capacitors should be connected on V
CAP_1
and V
CAP_2
pin. Refer to
Figure 17: Power supply scheme and Table 15: VCAP1/VCAP2 operating conditions.
All packages have the regulator ON feature.
3.16.2 Regulator OFF
This feature is available only on packages featuring the REGOFF pin. The regulator is
disabled by holding REGOFF high. The regulator OFF mode allows to supply externally a
V12 voltage source through V
CAP_1
and V
CAP_2
pins.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Figure 17: Power supply scheme.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic
power domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used at power-on reset. As a
consequence, PA0 and NRST pins must be managed separately if the debug
connection at reset or pre-reset is required.
Regulator OFF/internal reset ON
On UFBGA176 package, REGOFF must be connected to V
DD
.
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through V
CAP_1
and V
CAP_2
pins, in addition to V
DD
.