Datasheet

DocID17050 Rev 9 171/175
STM32F21xxx Revision history
174
29-Oct-2012 8
Removed Figure 4. Compatible board design between STM32F10xx
and STM32F2xx for LQFP176 package.
Updated number of AHB buses in Section 2: Description and
Section 3.12: Clocks and startup.
Updated Note 2 below Figure 4: STM32F21x block diagram.
Changed System memory to System memory + OTP in Figure 14:
Memory map.
Added Note 1 below Table 15: VCAP1/VCAP2 operating conditions.
Updated V
DDA
and V
REF+
decouping capacitor in Figure 17: Power
supply scheme and updated Note 3.
Changed simplex mode into half-duplex mode in Section 3.24: Inter-
integrated sound (I
2
S).
Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and
DAC_OUT2, respectively.
Changed TIM2_CH1/TIM2_ETR into TIM2_CH1_ETR for PA0 and
PA5 in Table 9: Alternate function mapping.
Updated note applying to I
DD
(external clock and all peripheral
disabled) in Table 20: Typical and maximum current consumption in
Run mode, code with data processing
running from Flash memory
(ART accelerator disabled). Updated Note 3 below Table 21: Typical
and maximum current consumption in Sleep mode.
Removed f
HSE_ext
typical value in Table 27: High-speed external user
clock characteristics.
Updated master I2S clock jitter conditions and vlaues in Table 34:
PLLI2S (audio PLL) characteristics.
Updated equations in Section 6.3.11: PLL spread spectrum clock
generation (SSCG) characteristics.
Swapped TTL and CMOS port conditions for V
OL
and V
OH
in Table 46:
Output voltage characteristics. Updated V
IL(NRST)
and V
IH(NRST)
in
Table 48: NRST pin characteristics.
Updated Table 53: SPI characteristics and Table 54: I
2
S
characteristics.Removed note 1 related to measurement points below
Figure 40: SPI timing diagram - slave mode and CPHA = 1, Figure 41:
SPI timing diagram - master mode, and Figure 42: I
2
S slave timing
diagram (Philips protocol)
(1)
.
Updated t
HC
in Table 60: ULPI timing.
Updated Figure 46: Ethernet SMI timing diagram, Table 62: Dynamics
characteristics: Ethernet MAC signals for SMI and Table 63: Dynamics
characteristics: Ethernet MAC signals for RMII.
Update f
TRIG
in Table 65: ADC characteristics. Updated I
DDA
description in Table 67: DAC characteristics.
Updated note below Figure 51: Power supply and reference
decoupling (V
REF+
not connected to V
DDA
) and Figure 52: Power
supply and reference decoupling (V
REF+
connected to V
DDA
).
Replaced t
d(CLKL-NOEL)
by t
d(CLKH-NOEL)
in Table 75: Synchronous
multiplexed NOR/PSRAM read timings, Table 77: Synchronous non-
multiplexed NOR/PSRAM read timings, Figure 58: Synchronous
multiplexed NOR/PSRAM read timings and Figure 60: Synchronous
non-multiplexed NOR/PSRAM read timings.
Table 93. Document revision history (continued)
Date Revision Changes