Datasheet
Revision history STM32F21xxx
166/175 DocID17050 Rev 9
22-Apr-2011
4
(continued)
Updated t
res(TIM)
in Table 49: Characteristics of TIMx connected to the
APB1 domain. Modified t
res(TIM)
and f
EXT
Table 50: Characteristics of
TIMx connected to the APB2 domain.
Changed t
w(SCKH)
to t
w(SCLH)
, t
w(SCKL)
to t
w(SCLL)
, t
r(SCK)
to t
r(SCL)
, and
t
f(SCK)
to t
f(SCL)
in Table 51: I
2
C characteristics and Figure 38: I
2
C bus
AC waveforms and measurement circuit.
Added Table 56: USB OTG FS DC electrical characteristics and
updated Table 57: USB OTG FS electrical characteristics.
Updated V
DD
minimum value in Table 61: Ethernet DC electrical
characteristics.
Updated Table 65: ADC characteristics and R
AIN
equation.
Updated R
AIN
equation. Updated Table 67: DAC characteristics.
Updated t
START
in Table 68: TS characteristics.
Updated Table 70: Embedded internal reference voltage.
Modified FSMC_NOE waveform in Figure 54: Asynchronous non-
multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed t
d(CLKH-NExH
) to t
d(CLKL-NExH)
,
t
d(CLKH-AIV)
to t
d(CLKL-
AIV)
, t
d(CLKH-NOEH)
to t
d(CLKL-NOEH)
, and t
d(CLKH-NWEH)
to t
d(CLKL-
NWEH)
, and updated data latency from 1 to 0 in Figure 58:
Synchronous multiplexed NOR/PSRAM read timings, Figure 59:
Synchronous multiplexed PSRAM write timings, Figure 60:
Synchronous non-multiplexed NOR/PSRAM read timings, and
Figure 61: Synchronous non-multiplexed PSRAM write timings,
Changed t
d(CLKH-NExH
) to t
d(CLKL-NExH)
,
t
d(CLKH-AIV)
to t
d(CLKL-AIV)
,
t
d(CLKH-NOEH)
to t
d(CLKL-NOEH)
, t
d(CLKH-NWEH)
to t
d(CLKL-NWEH)
, and
modified t
w(CLK)
minimum value in Table 75, Table 76, Table 77, and
Table 78 .
Updated R typical value in Table 69: V
BAT
monitoring
characteristics.Updated note 2 in Table 71 , Table 72, Table 73,
Table 74 , Table 75, Table 76, Ta ble 7 7, and Tabl e 78 .
Modified t
h(NIOWR-D)
in Figure 67: PC Card/CompactFlash controller
waveforms for I/O space write access.
Modified FSMC_NCEx signal in Figure 68: NAND controller
waveforms for read access, Figure 69: NAND controller waveforms for
write access, Figure 70: NAND controller waveforms for common
memory read access, and Figure 71: NAND controller waveforms for
common memory write access.
Specified Full speed (FS) mode for Figure 86: USB OTG HS
peripheral-only connection in FS mode and Figure 87: USB OTG HS
host-only connection in FS mode.
Table 93. Document revision history (continued)
Date Revision Changes