Datasheet

Revision history STM32F21xxx
164/175 DocID17050 Rev 9
22-Apr-2011 4
Changed datasheet status to “Full Datasheet”.
APB1 frequency changed form 36 MHz to 30 MHz.
Introduced concept of SRAM1 and SRAM2.
LQFP176 now in production.
Removed WLCSP64+2 package.
Updated Figure 3: Compatible board design between STM32F10xx
and STM32F2xx for LQFP144 package and Figure 2: Compatible
board design between STM32F10xx and STM32F2xx for LQFP100
package.
Added camera interface for STM32F217Vx devices in Table 2:
STM32F215xx and STM32F217xx: features and peripheral counts.
Removed 16 MHz internal RC oscillator accuracy in Section 3.12:
Clocks and startup.
Updated Section 3.16: Voltage regulator.
Modified I
2
S sampling frequency range in Section 3.12: Clocks and
startup, Section 3.24: Inter-integrated sound (I
2
S), and Section 3.30:
Audio PLL (PLLI2S).
Updated Section 3.17: Real-time clock (RTC), backup SRAM and
backup registers and description of TIM2 and TIM5 in Section 3.20.2:
General-purpose timers (TIMx).
Modified maximum baud rate (oversampling by 16) for USART1 in
Table 5: USART feature comparison.
Updated note related to RFU pin below Figure 10: STM32F21x
LQFP100 pinout, Figure 11: STM32F21x LQFP144 pinout, Figure 12:
STM32F21x LQFP176 pinout, Figure 13: STM32F21x UFBGA176
ballout, and Table 7: STM32F21x pin and ball definitions.
Added RTC_50Hz as PB15 alternate function, and TT (3.6 V tolerant
I/O) in Table 7: STM32F21x pin and ball definitions and Table 9:
Alternate function mapping.
PA15 added in Table 7: STM32F21x pin and ball definitions.
In Table 7: STM32F21x pin and ball definitions, changed I2S2_CK and
I2S3_CK to I2S2_SCK and I2S3_SCK, respectively.
Removed
ETH _RMII_TX_CLK for PC3/AF11 in
Table 9: Alternate
function mapping.
Updated Table 10: Voltage characteristics and Table 11: Current
characteristics.
T
STG
updated to –65 to +150 in Table 12: Thermal characteristics.
Added CEXT and ESR in Table 13: General operating conditions as
well as Section 6.3.2: VCAP1/VCAP2 external capacitor.
Modified Note 3 in Table 14: Limitations depending on the operating
power supply range.
Updated Table 16: Operating conditions at power-up / power-down
(regulator ON), and Table 17: Operating conditions at power-up /
power-down (regulator OFF).
Updated notes below and added OSC_OUT pin in Figure 15: Pin
loading conditions. and Figure 16: Pin input voltage.
Updated V
PVD
, V
BOR1
, V
BOR2
, V
BOR3
, T
RSTTEMPO
typical value, and
I
RUSH
, added E
RUSH
and Note 2 in Table 18: Embedded reset and
power control block characteristics.
Table 93. Document revision history (continued)
Date Revision Changes