Datasheet

DocID15818 Rev 11 145/178
STM32F20xxx Electrical characteristics
177
NAND controller waveforms and timings
Figure 70 through Figure 73 represent synchronous waveforms, together with Table 82 and
Table 83 provides the corresponding timings. The results shown in this table are obtained
with the following FSMC configuration:
• COM.FSMC_SetupTime = 0x01;
• COM.FSMC_WaitSetupTime = 0x03;
• COM.FSMC_HoldSetupTime = 0x02;
• COM.FSMC_HiZSetupTime = 0x01;
• ATT.FSMC_SetupTime = 0x01;
• ATT.FSMC_WaitSetupTime = 0x03;
• ATT.FSMC_HoldSetupTime = 0x02;
• ATT.FSMC_HiZSetupTime = 0x01;
• Bank = FSMC_Bank_NAND;
• MemoryDataWidth = FSMC_MemoryDataWidth_16b;
• ECC = FSMC_ECC_Enable;
• ECCPageSize = FSMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0;
In all timing tables, the
T
HCLK
is the HCLK clock period.
Table 81. Switching characteristics for PC Card/CF read and write cycles in I/O space
(1)(2)
Symbol Parameter Min Max Unit
t
w(NIOWR)
FSMC_NIOWR low width 8T
HCLK
- 0.5 - ns
t
v(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid - 5T
HCLK
- 1 ns
t
h(NIOWR-D)
FSMC_NIOWR high to FSMC_D[15:0] invalid 8T
HCLK
- 3 - ns
t
d(NCE4_1-NIOWR)
FSMC_NCE4_1 low to FSMC_NIOWR valid - 5T
HCLK
+ 1.5 ns
t
h(NCEx-NIOWR)
FSMC_NCEx high to FSMC_NIOWR invalid 5T
HCLK
-ns
t
d(NIORD-NCEx)
FSMC_NCEx low to FSMC_NIORD valid - 5T
HCLK
+ 1 ns
t
h(NCEx-NIORD)
FSMC_NCEx high to FSMC_NIORD) valid 5T
HCLK
– 0.5 - ns
t
w(NIORD)
FSMC_NIORD low width 8T
HCLK
+ 1 - ns
t
su(D-NIORD)
FSMC_D[15:0] valid before FSMC_NIORD
high
9.5 ns
t
d(NIORD-D)
FSMC_D[15:0] valid after FSMC_NIORD high 0 ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.