Datasheet

DocID15818 Rev 11 139/178
STM32F20xxx Electrical characteristics
177
Figure 63. Synchronous non-multiplexed PSRAM write timings
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Table 79. Synchronous non-multiplexed PSRAM write timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 2T
HCLK
- 1 - ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns
t
d(CLKL-
NADVL)
FSMC_CLK low to FSMC_NADV low - 5 ns
t
d(CLKL-
NADVH)
FSMC_CLK low to FSMC_NADV high 6 - ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low - 1 ns
t
d(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high 1 - ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NWE
FSMC_D[15:0]
D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-AV)
t
d(CLKL-AIV)
t
d(CLKL-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14993g
FSMC_NADV
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
d(CLKL-Data)
FSMC_NBL
t
d(CLKL-NBLH)