Datasheet

Electrical characteristics STM32F105xx, STM32F107xx
68/104 Doc ID 15274 Rev 6
Table 44. I
2
S characteristics
Symbol Parameter Conditions Min Max Unit
f
CK
1/t
c(CK)
I
2
S clock frequency
Master data: 16 bits, audio
freq = 48 K
1.52 1.54
MHz
Slave 0 6.5
t
r(CK)
t
f(CK)
I
2
S clock rise and fall time capacitive load C
L
= 50 pF 8
ns
t
w(CKH)
(1)
I
2
S clock high time
Master f
PCLK
= 16 MHz,
audio freq = 48 K
317 320
t
w(CKL)
(1)
I
2
S clock low time 333 336
t
v(WS)
(1)
WS valid time Master mode 3
t
h(WS)
(1)
WS hold time Master mode
I2S2 0
I2S3 0
t
su(WS)
(1)
WS setup time Slave mode
I2S2 4
I2S3 9
t
h(WS)
(1)
WS hold time Slave mode 0
DuCy(SCK)
I2S slave input clock duty
cycle
Slave mode 30 70
%
t
su(SD_MR)
(1)
Data input setup time
Master receiver
I2S2 8
ns
I2S3 10
t
su(SD_SR)
(1)
Slave receiver
I2S2 3
I2S3 8
t
h(SD_MR)
(1)
Data input hold time
Master receiver
I2S2 2
I2S3 4
t
h(SD_SR)
(1)
Slave receiver
I2S2 2
I2S3 4
t
v(SD_ST)
(1)(3)
Data output valid time
Slave transmitter
(after enable edge)
I2S2 23
I2S3 33
t
h(SD_ST)
(1)
Data output hold time
Slave transmitter
(after enable edge)
I2S2 29
I2S3 27
t
v(SD_MT)
(1)
Data output valid time
Master transmitter
(after enable edge)
I2S2 5
I2S3
2
t
h(SD_MT)
(1)
Data output hold time
Master transmitter
(after enable edge)
I2S2
11
I2S3
4
1. Based on design simulation and/or characterization results, not tested in production.