Datasheet

STM32F103xF, STM32F103xG Electrical characteristics
Doc ID 16554 Rev 3 95/120
Figure 49. SPI timing diagram - master mode
(1)
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
ai14136
SCK Input
CPHA= 0
MOSI
OUTUT
MISO
INP UT
CPHA= 0
MSBIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B IT1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK Input
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)