Datasheet

Electrical characteristics STM32F103xF, STM32F103xG
70/120 Doc ID 16554 Rev 3
Table 37. Synchronous multiplexed PSRAM write timings
(1)
1. C
L
= 15 pF.
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 27.5 - ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_Nex low (x = 0...2) - 0 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2) 1 - ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low - 1 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 1 - ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 1 - ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low - 1 ns
t
d(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high 1.5 - ns
t
d(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid - 10 ns
t
d(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid 1 - ns
t
d(CLKL-Data)
FSMC_A/D[15:0] valid after FSMC_CLK low - 6 ns
t
d(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high 1 - ns