Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 72 MHz I/O number 80

Target specification

This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.

January 2012 Doc ID 16554 Rev 3 1/120

STM32F103xF

STM32F103xG

XL-density performance line ARM-based 32-bit MCU with 768 KB to

1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU with MPU

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

■ Memories

– 768 Kbytes to 1 Mbyte of Flash memory

– 96 Kbytes of SRAM

– Flexible static memory controller with 4

Chip Select. Supports Compact Flash,

SRAM, PSRAM, NOR and NAND

memories

– LCD parallel interface, 8080/6800 modes

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

■ 3 × 12-bit, 1 µs A/D converters (up to 21

channels)

– Conversion range: 0 to 3.6 V

– Triple-sample and hold capability

– Temperature sensor

■ 2 × 12-bit D/A converters

■ DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

SDIO, I

Ss, SPIs, I

Cs and USARTs

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

– Cortex-M3 Embedded Trace Macrocell™

■ Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors and almost all

5 V-tolerant

■ Up to 17 timers

– Up to ten 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– 2 × 16-bit motor control PWM timers with

dead-time generation and emergency stop

– 2 × watchdog timers (Independent and

Window)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

■ Up to 13 communication interfaces

– Up to 2 × I

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 3 SPIs (18 Mbit/s), 2 with I

interface multiplexed

– CAN interface (2.0B Active)

– USB 2.0 full speed interface

– SDIO interface

■ CRC calculation unit, 96-bit unique ID

■ ECOPACK

packages

Table 1. Device summary

Reference Part number

STM32F103xF

STM32F103RF STM32F103VF

STM32F103ZF

STM32F103xG

STM32F103RG STM32F103VG

STM32F103ZG

FBGA

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm,

LQFP144 20 × 20 mm

LFBGA144 10 × 10 mm

www.st.com

Summary of content (120 pages)

PAGE 1
STM32F103xF STM32F103xG XL-density performance line ARM-based 32-bit MCU with 768 KB to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces Target specification Features FBGA ■ Core: ARM 32-bit Cortex™-M3 CPU with MPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.
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Contents STM32F103xF, STM32F103xG Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2/120 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview .
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STM32F103xF, STM32F103xG Contents 2.3.29 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.30 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.31 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . .
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Contents 6 STM32F103xF, STM32F103xG 5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1 Package mechanical data . . . . . . . . . . . . . .
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STM32F103xF, STM32F103xG List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . .
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List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. 6/120 STM32F103xF, STM32F103xG EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 EMI characteristics . . . . . .
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STM32F103xF, STM32F103xG List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39.
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List of figures Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. 8/120 STM32F103xF, STM32F103xG Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F103xF, STM32F103xG 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xF and STM32F103xG XL-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The XL-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual.
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Description 2 STM32F103xF, STM32F103xG Description The STM32F103xF and STM32F103xG performance line family incorporates the highperformance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM up to 96 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
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STM32F103xF, STM32F103xG 2.1 Description Device overview The STM32F103xx XL-density performance line family offers devices in four different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2.
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Description TRACECLK TRACED[0:3] as AF NJTRST JTDI JTCK/SWCLK JTMS/SWDAT JTDO as AF TPIU SWJTAG Flash obl interface STM32F103xF and STM32F103xG performance line block diagram ETM Trace/Trig Ib u s Cortex-M3 CPU Fmax: 48/72 MHz NVIC Dbus 64 bit Bus matrix GP DMA1 64 bit @VDDA RC HS SRAM 96 Kbyte RC LS IWDG GP DMA2 5 channels Reset & clock controller PCLK1 PCLK2 PCLK3 HCLK FCLK SDIO XTAL 32 kHz RTC AWU GPIO port D PE[15:0] GPIO port E PF[15:0] GPIO port F 8 ADINs common to the 3 ADCs
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STM32F103xF, STM32F103xG Figure 2. Description Clock tree FLITFCLK to Flash programming interface USB Prescaler /1, 1.5 USBCLK to USB interface 48 MHz I2S3CLK Peripheral clock enable 8 MHz HSI RC I2S2CLK to I2S2 Peripheral clock enable Peripheral clock enable HSI SDIOCLK FSMCCLK Peripheral clock enable 72 MHz max /2 PLLSRC to I2S3 /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK 72 MHz max PLLCLK AHB Prescaler /1, 2..
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Description 2.2 STM32F103xF, STM32F103xG Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible.
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STM32F103xF, STM32F103xG Description 2.3 Overview 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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Description 2.3.5 STM32F103xF, STM32F103xG Embedded SRAM 96 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.6 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F103xF and STM32F103xG performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: 2.3.
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STM32F103xF, STM32F103xG 2.3.10 Description Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled.
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Description 2.3.14 STM32F103xF, STM32F103xG Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● MR is used in the nominal regulation mode (Run) ● LPR is used in the Stop modes. ● Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset.
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STM32F103xF, STM32F103xG Description The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I2S, SDIO and ADC. 2.3.17 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present.
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Description STM32F103xF, STM32F103xG Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer.
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STM32F103xF, STM32F103xG Description Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes.
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Description 2.3.21 STM32F103xF, STM32F103xG Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.
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STM32F103xF, STM32F103xG Description The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2.3.27 ADC (analog to digital converter) Three 12-bit analog-to-digital converters are embedded into STM32F103xF and STM32F103xG performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes.
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Description 2.3.29 STM32F103xF, STM32F103xG Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.
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STM32F103xF, STM32F103xG Pinouts and pin descriptions 3 Pinouts and pin descriptions Figure 3.
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Pinouts and pin descriptions STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4.
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STM32F103xF, STM32F103xG STM32F103xF and STM32F103xG XL-density performance line LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 5.
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Pinouts and pin descriptions STM32F103xF and STM32F103xG XL-density performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 6.
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STM32F103xF, STM32F103xG Table 5.
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Pinouts and pin descriptions STM32F103xF and STM32F103xG pin definitions (continued) LQFP100 - 21 32 Pin name Type(1) LQFP64 L1 LQFP144 LFBGA144 Pins I / O level(2) Table 5.
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STM32F103xF, STM32F103xG STM32F103xF and STM32F103xG pin definitions (continued) Alternate functions(4) LQFP100 LQFP144 Default LQFP64 Main function(3) (after reset) LFBGA144 Type(1) Pins I / O level(2) Table 5.
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Pinouts and pin descriptions STM32F103xF and STM32F103xG pin definitions (continued) Alternate functions(4) Remap PD13 FSMC_A18 TIM4_CH2 K10 - 60 82 G8 - - 83 VSS_8 S VSS_8 F8 - - 84 VDD_8 S VDD_8 K11 - 61 85 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3 K12 - 62 86 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4 J12 - - 87 PG2 I/O FT PG2 FSMC_A12 J11 - - 88 PG3 I/O FT PG3 FSMC_A13 J10 - - 89 PG4 I/O FT PG4 FSMC_A14 H12 - - 90 PG5 I/O FT PG5 FSMC_A15 H11 - - 9
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STM32F103xF, STM32F103xG STM32F103xF and STM32F103xG pin definitions (continued) Pin name Type(1) LQFP144 LQFP100 LQFP64 LFBGA144 Pins I / O level(2) Table 5.
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Pinouts and pin descriptions STM32F103xF and STM32F103xG pin definitions (continued) Pin name Type(1) LQFP144 LQFP100 LQFP64 LFBGA144 Pins I / O level(2) Table 5.
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STM32F103xF, STM32F103xG Table 6.
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Pinouts and pin descriptions Table 6.
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STM32F103xF, STM32F103xG 4 Memory mapping Memory mapping The memory map is shown in Figure 7. Figure 7.
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Electrical characteristics STM32F103xF, STM32F103xG 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 39
STM32F103xF, STM32F103xG 5.1.6 Electrical characteristics Power supply scheme Figure 10. Power supply scheme 6"!4 "ACKUP CIRCUITRY /3# + 24# 7AKE UP LOGIC "ACKUP REGISTERS /54 '0 ) /S ). ,EVEL SHIFTER 0O WER SWI TCH 6 )/ ,OGIC +ERNEL LOGIC #05 $IGITAL -EMORIES 6$$ 6$$ 2EGULATOR § N& § & 633 6$$ 6$$! 62%& N& & N& & 62%& 62%& !$# $!# !NALOG 2#S 0,, 633! AI Caution: In Figure 10, the 4.
PAGE 40
Electrical characteristics 5.2 STM32F103xF, STM32F103xG Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7.
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STM32F103xF, STM32F103xG Table 9. Electrical characteristics Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Table 10. Value Unit –65 to +150 °C 150 °C General operating conditions Symbol Parameter fHCLK Min Max Internal AHB clock frequency 0 72 fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 72 Standard operating voltage 2 3.
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Electrical characteristics 5.3.2 STM32F103xF, STM32F103xG Operating conditions at power-up / power-down The parameters given in Table 11 are derived from tests performed under the ambient temperature condition summarized in Table 10. Table 11. Operating conditions at power-up / power-down Symbol Parameter tVDD 5.3.
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STM32F103xF, STM32F103xG 5.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 13. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.24 V - 5.1 17.
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Electrical characteristics Table 14. STM32F103xF, STM32F103xG Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Run mode fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 68 69 48 MHz 51 51 36 MHz 41 41 24 MHz 29 30 16 MHz 22 22.5 8 MHz 12.5 14 72 MHz 39 39 48 MHz 29.5 30 24 24.5 17.5 19 16 MHz 14 15 8 MHz 8.5 10.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled #ONSUMPTION M! -(Z -(Z -(Z -(Z -(Z -(Z 4EMPERATURE # AI Figure 13. Typical current consumption in Run mode versus frequency (at 3.
PAGE 46
Electrical characteristics Table 16. STM32F103xF, STM32F103xG Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 47.5 48.5 48 MHz 34 35 36 MHz 27.5 27.5 24 MHz 20 20.5 16 MHz 15 16 8 MHz 9 11 72 MHz 9.5 11.2 48 MHz 7.7 9.5 36 MHz 6.9 8.5 24 MHz 5.9 7.8 16 MHz 5.4 7.2 8 MHz 4.7 6.
PAGE 47
STM32F103xF, STM32F103xG Table 17. Electrical characteristics Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol IDD IDD_VBAT Parameter Conditions Max VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = = 2.0 V = 2.4 V = 3.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 15.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 16. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values #ONSUMPTION μ! 6 6 6 6 6 # # # 4EMPERATURE # # AI Figure 17.
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Electrical characteristics STM32F103xF, STM32F103xG Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load). ● All peripherals are disabled except if it is explicitly mentioned. ● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above). ● Ambient temperature and VDD supply voltage conditions summarized in Table 10.
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STM32F103xF, STM32F103xG Table 19. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions External clock IDD Supply current in Sleep mode (3) fHCLK All peripherals All peripherals enabled(2) disabled 72 MHz 32.5 7 48 MHz 23 5 36 MHz 17.7 4 24 MHz 12.2 3.1 16 MHz 8.4 2.3 8 MHz 4.6 1.5 4 MHz 3 1.3 2 MHz 2.15 1.25 1 MHz 1.7 1.2 500 kHz 1.5 1.15 125 kHz 1.35 1.15 64 MHz 28.7 5.
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Electrical characteristics STM32F103xF, STM32F103xG On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 20.
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STM32F103xF, STM32F103xG Table 20. Electrical characteristics Peripheral current consumption(1) (continued) Peripheral APB2 Typical consumption at 25 °C GPIOA 0.55 GPIOB 0.55 GPIOC 0.55 GPIOD 0.6 GPIOE 0.6 GPIOF 0.55 GPIOG 0.55 TIM1 1.95 TIM8 1.9 TIM9 1 TIM10 0.8 TIM11 0.8 ADC1(3) 1.85 ADC2(3) 1.8 ADC3(3) 1.8 SPI1 0.45 USART1 0.8 Unit mA 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2.
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Electrical characteristics Table 21. STM32F103xF, STM32F103xG High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 25 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 18. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Figure 19.
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Electrical characteristics STM32F103xF, STM32F103xG High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23.
PAGE 57
STM32F103xF, STM32F103xG Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 21. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator CL2 Bias controlled gain RF STM32F103xx OSC32_OU T ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 25.
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STM32F103xF, STM32F103xG Electrical characteristics Low-speed internal (LSI) RC oscillator Table 26. LSI oscillator characteristics (1) Symbol fLSI(2) Parameter Frequency Min Typ Max Unit 30 40 60 kHz tsu(LSI)(3) LSI oscillator startup time - - 85 µs IDD(LSI)(3) LSI oscillator power consumption - 0.65 1.2 µA 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
PAGE 60
Electrical characteristics 5.3.8 STM32F103xF, STM32F103xG PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 1 8.
PAGE 61
STM32F103xF, STM32F103xG Table 30. Electrical characteristics Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle (2) 10 kcycles at TA = 105 °C 10 (2) 20 at TA = 55 °C Unit kcycles Years 1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range. 5.
PAGE 62
Electrical characteristics STM32F103xF, STM32F103xG Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &3-#?.% T V ./%?.% T W ./% T H .%?./% &3-#?./% &3-#?.7% TV !?.% &3-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &3-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &3-#?$; = T V .!$6?.% TW .!$6 &3-#?.!$6 -3 6 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Note: 62/120 FSMC_BusTurnAroundDuration = 0.
PAGE 63
STM32F103xF, STM32F103xG Electrical characteristics Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Table 31. Symbol Parameter Min Max Unit 5tHCLK + 0.5 5tHCLK + 2 ns 0.5 1.
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Electrical characteristics Table 32. Symbol STM32F103xF, STM32F103xG Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Parameter Min Max Unit tw(NE) FSMC_NE low time 3tHCLK + 0.5 3tHCLK + 1.5 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK + 0.5 tHCLK + 1.5 ns tw(NWE) FSMC_NWE low time tHCLK – 0.5 tHCLK + 1 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK – 0.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 34.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 35. Symbol Asynchronous multiplexed PSRAM/NOR write timings(1) Parameter Max Unit 5tHCLK + 0.
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STM32F103xF, STM32F103xG Electrical characteristics Synchronous waveforms and timings Figure 26 through Figure 29 represent synchronous waveforms and Table 37 through Table 39 provide the corresponding timings.
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Electrical characteristics Table 36. STM32F103xF, STM32F103xG Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Parameter Max Unit 27.6 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 0...
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STM32F103xF, STM32F103xG Electrical characteristics Figure 27. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, !$)6 TD #,+, $ATA TD #,+, $ATA TD #,+, !$6 !$; = &3-#?!$; = $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+, .",( &3-#?.
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Electrical characteristics Table 37. STM32F103xF, STM32F103xG Synchronous multiplexed PSRAM write timings(1) Symbol Parameter Max Unit 27.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 1 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...
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STM32F103xF, STM32F103xG Electrical characteristics Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !)6 TD #,+, !6 &3-#?!; = TD #,+, ./%, TD #,+, ./%( &3-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( $ &3-#?$; = TSU .7!)46 #,+( TH #,+( $6 $ $ TH #,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( T H #,+( .7!)46 &3-#?.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 29. Synchronous non-multiplexed PSRAM write timings TW #,+ "53452. TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, $ATA &3-#?$; = TD #,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TD #,+, .",( TH #,+( .7!)46 &3-#?.", AI H Table 39.
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STM32F103xF, STM32F103xG Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 30 through Figure 35 represent synchronous waveforms and Table 42 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime = 0x00; ● ATT.FSMC_SetupTime = 0x04; ● ATT.FSMC_WaitSetupTime = 0x07; ● ATT.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 31.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 32. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded).
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Electrical characteristics STM32F103xF, STM32F103xG Figure 33. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 34.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 35. PC Card/CompactFlash controller waveforms for I/O space write access &3-#?.#% ? &3-#?.#% ? TV .#%X ! TH .#% ? !) &3-#?!; = &3-#?.2%' &3-#?.7% &3-#?./% &3-#?.)/2$ TD .#% ? .)/72 TW .)/72 &3-#?.)/72 !44X(): TV .)/72 $ TH .)/72 $ &3-#?$; = AI B Table 40.
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Electrical characteristics Table 41. STM32F103xF, STM32F103xG Switching characteristics for PC Card/CF read and write cycles in I/O space Symbol Parameter tw(NIOWR) Min Max Unit 8 THCLK - ns - 5 THCLK 4 ns 11THCLK 7 - ns FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK + 1 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK 2.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 36. NAND controller waveforms for read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) th(NOE-ALE) FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14901b Figure 37. NAND controller waveforms for write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) th(NWE-ALE) FSMC_NWE FSMC_NOE (NRE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14902b Figure 38.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 39. NAND controller waveforms for common memory write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FSMC_NWE FSMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14913b Table 42.
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STM32F103xF, STM32F103xG 5.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32F103xF, STM32F103xG Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be appFlied directly on the device, over the range of specification values.
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STM32F103xF, STM32F103xG Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 47. Symbol LU 5.3.
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Electrical characteristics 5.3.14 STM32F103xF, STM32F103xG I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 49. Symbol VIL VIH Vhys Ilkg I/O static characteristics Parameter Min Typ Max Unit Standard IO input low level voltage –0.3 - 0.28*(VDD-2 V)+0.8 V V IO FT(1) input low level voltage –0.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 40. Standard I/O input characteristics - CMOS port 6)( 6), 6 6 $$ ENT 6 )( #-/3 7)(MIN 7),MAX 6 6 )( $$ QUIREM NDARD RE T 6 ), 6 $$ 6 ), 6 ## RD REQUIREMEN #-/3 STANDA )NPUT RANGE NOT GUARANTEED STA 6$$ 6 AI B Figure 41.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 42. 5 V tolerant I/O input characteristics - CMOS port 6)( 6), 6 6 $$ TS 6 )( UIREMEN ARD REQ 3 STAND #-/ 6 ), 6 $$ T 6 ), 6 $$ REQUIRMEN /3 STANDARD #- 6 )( 6 $$ )NPUT RANGE NOT GUARANTEED 6$$ 6 6$$ AI B Figure 43.
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STM32F103xF, STM32F103xG Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 50.
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Electrical characteristics STM32F103xF, STM32F103xG Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 44 and Table 51, respectively. Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 51.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 44. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 49).
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Electrical characteristics 5.3.16 STM32F103xF, STM32F103xG TIM timer characteristics The parameters given in Table 53 are guaranteed by design. Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 53. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max Unit 1 - tTIMxCLK 13.
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STM32F103xF, STM32F103xG 5.3.17 Electrical characteristics Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 54 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 10.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 46. I2C bus AC waveforms and measurement circuit VDD VDD 4 .7 k 4 .7 k STM32F103xx 100 SDA I2C bus 100 SCL S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) th(STA) SCL tw(SCLH) tsu(SDA) tw(SCLL) tr(SCL) th(SDA) tw(STO:STA) S TOP tsu(STO) tf(SCL) ai14149c 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 55. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.
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STM32F103xF, STM32F103xG Electrical characteristics I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 56 for SPI or in Table 57 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 56.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 47. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) tSU(NSS) SCK Input CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 48.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 49. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MS BIN tr(SCK) tf(SCK) BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics Table 57. STM32F103xF, STM32F103xG I2S characteristics Symbol DuCy(SCK) Parameter Conditions Min Max Unit 30 70 % 1.522 1.525 Slave mode 0 6.
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STM32F103xF, STM32F103xG Electrical characteristics Figure 50. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2.
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Electrical characteristics STM32F103xF, STM32F103xG SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 52.
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STM32F103xF, STM32F103xG Table 58.
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Electrical characteristics Table 60. STM32F103xF, STM32F103xG USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V V Input levels VDD (4) USB operating voltage(2) I(USBDP, USBDM) 0.2 VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 VDI Differential input sensitivity Output levels VOL Static output level low RL of 1.5 kΩ to 3.
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STM32F103xF, STM32F103xG 5.3.19 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 62 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Note: It is recommended to perform a calibration after each power-up. Table 62. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 - 3.
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Electrical characteristics STM32F103xF, STM32F103xG Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 63. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.
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STM32F103xF, STM32F103xG Table 65. Electrical characteristics ADC accuracy(1) (2)(3) Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
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Electrical characteristics STM32F103xF, STM32F103xG Figure 56. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL±1 µA STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14150c 1. Refer to Table 62 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
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STM32F103xF, STM32F103xG Electrical characteristics Figure 58. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai14389 1. VREF+ and VREF– inputs are available only on 100-pin packages.
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Electrical characteristics STM32F103xF, STM32F103xG 5.3.20 DAC electrical specifications Table 66. DAC characteristics Symbol Parameter Min Typ Max Unit VDDA Analog supply voltage 2.4 - 3.6 V VREF+ Reference supply voltage 2.4 - 3.6 V VSSA Ground 0 - 0 V Resistive load vs. VSSA with buffer ON 5 - - kΩ Resistive load vs.
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STM32F103xF, STM32F103xG Table 66.
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Electrical characteristics 5.3.21 STM32F103xF, STM32F103xG Temperature sensor characteristics Table 67. TS characteristics Symbol TL(1) Avg_Slope V25 Parameter Min Typ Max Unit - ±1 ±2 °C Average slope 4.0 4.3 4.6 mV/°C Voltage at 25 °C 1.34 1.43 1.52 V VSENSE linearity with temperature (1) (1) tSTART(2) Startup time 4 - 10 µs TS_temp(3)(2) ADC sampling time when reading the temperature - - 17.1 µs 1. Based on characterization, not tested in production. 2.
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STM32F103xF, STM32F103xG Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 60. Recommended PCB design rules (0.80/0.75 mm pitch BGA Dpad Dpad 0.37 mm Dsm 0.52 mm typ.
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Package characteristics STM32F103xF, STM32F103xG Figure 61. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline C Seating plane A2 ddd A4 C A A3 A1 B D D1 A e F M F E1 E e Øb (144 balls) Ball A1 Ø eee M C A Ø fff M B C X3_ME 1. Drawing is not to scale. Table 68. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data inches(1) millimeters Symbol Min Typ A A1 Max Typ 1.70 0.21 Max 0.
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STM32F103xF, STM32F103xG Package characteristics Figure 62. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline(1) Figure 63. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.25 mm gage plane C 108 109 D 73 1.35 72 0.35 k D1 0.5 A1 D3 L 73 108 L1 17.85 19.9 22.6 72 109 144 E1 E 37 1 36 E3 19.9 22.6 ai149 144 Pin 1 identification 37 36 1 e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 69.
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Package characteristics STM32F103xF, STM32F103xG Figure 64. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline(1) Figure 65. Recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE k 75 51 D L D1 76 L1 D3 51 75 50 0.5 C 76 50 0.3 16.7 14.3 b E3 E1 E 100 26 1.2 100 26 Pin 1 1 identification 1 25 ccc 25 C 12.3 e A1 16.7 ai14906b A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 70.
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STM32F103xF, STM32F103xG Package characteristics Figure 67. Recommended footprint(1)(2) Figure 66. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline(1) 48 33 D 0.3 ccc C D1 A A2 D3 33 48 49 32 49 12.7 32 0.5 10.3 b L1 10.3 E3 E1 E 64 L A1 K 1.2 64 1 17 Pin 1 identification 16 1 17 c 16 7.8 5W_ME 12.7 ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 71.
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Package characteristics 6.2 STM32F103xF, STM32F103xG Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 41.
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STM32F103xF, STM32F103xG 6.2.2 Package characteristics Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 73: STM32F103xF and STM32F103xG ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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Package characteristics STM32F103xF, STM32F103xG Using the values obtained in Table 72 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 73: STM32F103xF and STM32F103xG ordering information scheme). Figure 68. LQFP100 PD max vs.
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STM32F103xF, STM32F103xG 7 Part numbering Part numbering Table 73. STM32F103xF and STM32F103xG ordering information scheme Example: STM32 F103 RF T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size F = 768 Kbytes of Flash memory G = 1 Mbyte of Flash memory Package H = BGA T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C.
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Revision history 8 STM32F103xF, STM32F103xG Revision history Table 74. Document revision history Date Revision 27-Oct-2009 1 Initial release. 2 LQFP64 package mechanical data updated: see Figure 66: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline and Table 71: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. Internal code removed from Table 73: STM32F103xF and STM32F103xG ordering information scheme.
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STM32F103xF, STM32F103xG Table 74.
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STM32F103xF, STM32F103xG Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.