Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 32-Bit 72 MHz I/O number 80

This is information on a product in full production.

August 2013 DocID13587 Rev 16 1/105

STM32F103x8

STM32F103xB

Medium-density performance line ARM-based 32-bit MCU with 64

or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Datasheet - production data

Features

 ARM 32-bit Cortex™-M3 CPU Core

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

 Memories

– 64 or 128 Kbytes of Flash memory

– 20 Kbytes of SRAM

 Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

 Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

 2 x 12-bit, 1 µs A/D converters (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Dual-sample and hold capability

– Temperature sensor

 DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

Cs and USARTs

 Up to 80 fast I/O ports

– 26/37/51/80 I/Os, all mappable on 16

external interrupt vectors and almost all

5 V-tolerant

 Debug mode

– Serial wire debug (SWD) & JTAG

interfaces

 7 timers

– Three 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– 16-bit, motor control PWM timer with dead-

time generation and emergency stop

– 2 watchdog timers (Independent and

Window)

– SysTick timer 24-bit downcounter

 Up to 9 communication interfaces

– Up to 2 x I

C interfaces (SMBus/PMBus)

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 2 SPIs (18 Mbit/s)

– CAN interface (2.0B Active)

– USB 2.0 full-speed interface

 CRC calculation unit, 96-bit unique ID

 Packages are ECOPACK

Table 1. Device summary

Reference Part number

STM32F103x8

STM32F103C8, STM32F103R8

STM32F103V8, STM32F103T8

STM32F103xB

STM32F103RB STM32F103VB,

STM32F103CB, STM32F103TB

BGA100 10 × 10 mm

UFBGA100 7 x 7 mm

BGA64 5 × 5 mm

VFQFPN36 6 × 6 mm

LQFP100 14 × 14 mm

LQFP64 10 × 10 mm

LQFP48 7 × 7 mm

UFQFPN48 7 × 7 mm

www.st.com

Summary of content (105 pages)

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STM32F103x8 STM32F103xB Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces Datasheet - production data Features  ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and supply management – 2.0 to 3.
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Contents STM32F103x8, STM32F103xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Overview . . . .
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STM32F103x8, STM32F103xB 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 6 Contents Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.3 Typical curves . . . . . . . . . . . .
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Contents STM32F103x8, STM32F103xB 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F103x8, STM32F103xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . .
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. 6/105 STM32F103x8, STM32F103xB USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 RAIN max for fADC = 14 MHz . . . . . . .
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STM32F103x8, STM32F103xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. 8/105 STM32F103x8, STM32F103xB UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . .
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STM32F103x8, STM32F103xB 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual.
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Description 2.1 STM32F103x8, STM32F103xB Device overview Table 2.
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STM32F103x8, STM32F103xB Description Figure 1. STM32F103xx performance line block diagram TPIU SW/JTAG Trace Controlle r pbu s Trace/trig flash obl Inte rfac e Ibus Cortex-M3 CPU Fmax : 7 2M Hz Dbus Syst em NVIC AHB:F max =48/72 MHz @VDDA SUPPLY SUPERVISION NRST VDDA VSSA Rst PVD Int PCLK1 PCLK2 HCLK FCLK AHB2 APB2 @VDD PLL & CLOCK MANAGT XTAL OSC 4-16 MHz GPIOA GPIOB PC[15:0] GPIOC PD[15:0] GPIOD PE[15:0] GPIOE 4 Chann els 3 co mpl.
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Description STM32F103x8, STM32F103xB Figure 2. Clock tree FLITFCLK to Flash programming interface 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz 72 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..
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STM32F103x8, STM32F103xB 2.2 Description Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.
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Description STM32F103x8, STM32F103xB 2.3 Overview 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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STM32F103x8, STM32F103xB Description This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests.
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Description STM32F103x8, STM32F103xB in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold.
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STM32F103x8, STM32F103xB 2.3.13 Description DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel.
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Description STM32F103x8, STM32F103xB Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer.
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STM32F103x8, STM32F103xB Description SysTick timer This timer is dedicated for OS, but could also be used as a standard downcounter. It features: 2.3.16  A 24-bit downcounter  Autoreload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.
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Description 2.3.21 STM32F103x8, STM32F103xB GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.
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STM32F103x8, STM32F103xB 3 Pinouts and pin description Pinouts and pin description Figure 3.
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Pinouts and pin description STM32F103x8, STM32F103xB 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4.
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STM32F103x8, STM32F103xB Pinouts and pin description Figure 5.
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Pinouts and pin description STM32F103x8, STM32F103xB VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 6.
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STM32F103x8, STM32F103xB Pinouts and pin description Figure 7.
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Pinouts and pin description STM32F103x8, STM32F103xB VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 8.
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STM32F103x8, STM32F103xB Pinouts and pin description PB7 PB6 PB5 PB4 PB3 PA15 PA14 36 BOOT0 VSS_3 Figure 10.
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Pinouts and pin description STM32F103x8, STM32F103xB Table 5.
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STM32F103x8, STM32F103xB Pinouts and pin description Table 5.
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Pinouts and pin description STM32F103x8, STM32F103xB Table 5.
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STM32F103x8, STM32F103xB Pinouts and pin description Table 5.
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Pinouts and pin description STM32F103x8, STM32F103xB Table 5.
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STM32F103x8, STM32F103xB Pinouts and pin description Table 5.
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Memory mapping 4 STM32F103x8, STM32F103xB Memory mapping The memory map is shown in Figure 11. Figure 11.
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STM32F103x8, STM32F103xB Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics STM32F103x8, STM32F103xB Figure 12. Pin loading conditions Figure 13. Pin input voltage STM32F103xx pin STM32F103xx pin C = 50 pF VIN ai14141 5.1.6 ai14142 Power supply scheme Figure 14. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 × 100 nF + 1 × 4.
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STM32F103x8, STM32F103xB 5.1.7 Electrical characteristics Current consumption measurement Figure 15. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device.
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Electrical characteristics STM32F103x8, STM32F103xB Table 7. Current characteristics Symbol Ratings Max.
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STM32F103x8, STM32F103xB Electrical characteristics Table 9. General operating conditions (continued) Symbol Parameter Conditions Min Max –0.3 VDD+ 0.3 2 V < VDD  3.6 V –0.3 5.5 VDD = 2 V –0.3 5.2 0 5.
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Electrical characteristics 5.3.3 STM32F103x8, STM32F103xB Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11. Embedded reset and power control block characteristics Symbol Parameter VPVD Min Typ Max PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 PLS[2:0]=000 (falling edge) 2 2.08 2.16 PLS[2:0]=001 (rising edge) 2.19 2.28 2.
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STM32F103x8, STM32F103xB 5.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Embedded internal reference voltage Symbol VREFINT Parameter Internal reference voltage Conditions Min Typ Max –40 °C < TA < +105 °C 1.16 1.20 1.26 –40 °C < TA < +85 °C 1.16 1.20 1.24 5.1 17.
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Electrical characteristics STM32F103x8, STM32F103xB Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK TA = 105 °C 72 MHz 50 50.3 48 MHz 36.1 36.2 36 MHz 28.6 28.7 24 MHz 19.9 20.1 16 MHz 14.7 14.9 8 MHz 8.6 8.9 72 MHz 32.8 32.9 48 MHz 24.4 24.5 External clock(2), all 36 MHz peripherals disabled 24 MHz 19.8 19.9 13.9 14.2 16 MHz 10.7 11 8 MHz 6.8 7.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 16. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 45 40 Consumption (mA) 35 30 72 MHz 36 MHz 16 MHz 8 MHz 25 20 15 10 5 0 -40 0 25 70 85 105 Temperature (°C) Figure 17. Typical current consumption in Run mode versus frequency (at 3.
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Electrical characteristics STM32F103x8, STM32F103xB Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Max(1) TA = 85 °C TA = 105 °C 72 MHz 30 32 48 MHz 20 20.5 36 MHz 15.5 16 24 MHz 11.5 12 16 MHz 8.5 9 8 MHz 5.5 6 72 MHz 7.5 8 48 MHz 6 6.5 36 MHz 5 5.5 24 MHz 4.5 5 16 MHz 4 4.
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STM32F103x8, STM32F103xB Electrical characteristics Table 16. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2.0 V = 2.4 V = 3.
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Electrical characteristics STM32F103x8, STM32F103xB Figure 19. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V 300 Consumption (µA) 250 200 3.3 V 150 3.6 V 100 50 0 -45 25 70 90 110 Temperature (°C) Figure 20. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 300 Consumption (µA) 250 200 3.3 V 150 3.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 21. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 4.5 4 Consumption (µA) 3.5 3 2.5 3.3 V 2 3.6 V 1.5 1 0.5 0 –45 °C 25 °C 85 °C 105 °C Temperature (°C) Typical current consumption The MCU is placed under the following conditions:  All I/O pins are in input mode with a static value at VDD or VSS (no load).  All peripherals are disabled except if it is explicitly mentioned.
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Electrical characteristics STM32F103x8, STM32F103xB Table 17. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals disabled enabled(2) 72 MHz 36 27 48 MHz 24.2 18.6 36 MHz 19 14.8 24 MHz 12.9 10.1 16 MHz 9.3 7.4 8 MHz 5.5 4.6 4 MHz 3.3 2.
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STM32F103x8, STM32F103xB Electrical characteristics Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions External clock IDD Supply current in Sleep mode (3) fHCLK All peripherals All peripherals enabled(2) disabled 72 MHz 14.4 5.5 48 MHz 9.9 3.9 36 MHz 7.6 3.1 24 MHz 5.3 2.3 16 MHz 3.8 1.8 8 MHz 2.1 1.2 4 MHz 1.6 1.1 2 MHz 1.3 1 1 MHz 1.11 0.98 500 kHz 1.04 0.96 125 kHz 0.98 0.95 64 MHz 12.3 4.
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Electrical characteristics STM32F103x8, STM32F103xB On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19.
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STM32F103x8, STM32F103xB 5.3.6 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20.
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Electrical characteristics STM32F103x8, STM32F103xB Figure 22. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Figure 23.
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STM32F103x8, STM32F103xB Electrical characteristics Table 22. HSE 4-16 MHz oscillator characteristics(1) (2) Symbol Parameter Min Typ Max Unit Oscillator frequency 4 8 16 MHz RF Feedback resistor - 200 - k C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 - 30 - pF i2 HSE driving current VDD = 3.
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Electrical characteristics STM32F103x8, STM32F103xB Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2) Symbol Parameter Conditions Min Typ Max Unit - 5 - M RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS) RS = 30 K - - 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS - - 1.4 µA gm Oscillator transconductance 5 - - µA/V TA = 50 °C - 1.5 - TA = 25 °C - 2.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 25. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator Bias controlled gain RF STM32F103xx OSC32_OU T CL2 ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 24.
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Electrical characteristics STM32F103x8, STM32F103xB Low-speed internal (LSI) RC oscillator Table 25. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI)(3) IDD(LSI) (3) Parameter Min Typ Max Unit 30 40 60 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.65 1.2 µA Frequency 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
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STM32F103x8, STM32F103xB Electrical characteristics Table 26. Low-power mode wakeup timings Symbol Parameter tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Typ Wakeup from Sleep mode 1.8 Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low power mode) 5.4 Wakeup from Standby mode 50 Unit µs 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 5.3.
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Electrical characteristics STM32F103x8, STM32F103xB Table 28. Flash memory characteristics (continued) Symbol IDD Vprog Min(1) Typ Max(1) Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V - - 20 Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V - - 5 Power-down mode / Halt, VDD = 3.0 to 3.6 V - - 50 µA 2 - 3.6 V Parameter Supply current Conditions Programming voltage Unit mA 1. Guaranteed by design, not tested in production. Table 29.
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STM32F103x8, STM32F103xB Electrical characteristics Table 30. EMS characteristics Symbol Parameter Level/ Class Conditions VFESD VDD 3.3 V, TA +25 °C, Voltage limits to be applied on any I/O pin to fHCLK 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.
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Electrical characteristics 5.3.11 STM32F103x8, STM32F103xB Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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STM32F103x8, STM32F103xB 5.3.12 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
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Electrical characteristics 5.3.13 STM32F103x8, STM32F103xB I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35.
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STM32F103x8, STM32F103xB Electrical characteristics 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
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Electrical characteristics STM32F103x8, STM32F103xB All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 26 and Figure 27 for standard I/Os, and in Figure 28 and Figure 29 for 5 V tolerant I/Os. Figure 26. Standard I/O input characteristics - CMOS port Area not determined VIH/VIL (V) =0.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 28. 5 V tolerant I/O input characteristics - CMOS port Area not determined VIH/VIL (V) =0.65V DD nts V IH quireme dard re OS stan CM in Tested on producti 1.3 1 0.7 0.75 1.55 1.16 1.42 1.07 1.295 0.975 -2)+1 V IH=0.42(V DD simulations gn si de on d 1.67 Base -2)+0.75 1 V IL=0.32(V DD ions sign simulat Based on de 5V DD ent V IL =0.3 dard requirm CMOS stan oduction Tested in pr 2 2.7 3 3.3 VDD (V) 3.
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Electrical characteristics STM32F103x8, STM32F103xB Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
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STM32F103x8, STM32F103xB Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 30 and Table 37, respectively. Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37.
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Electrical characteristics STM32F103x8, STM32F103xB Figure 30. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON 50pF tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131c 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 35).
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STM32F103x8, STM32F103xB Electrical characteristics Figure 31. Recommended NRST pin protection VDD External reset circuit(1) RPU NRST(2) Internal reset Filter 0.1 µF STM32F10x ai14132d 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 38. Otherwise the reset will not be taken into account by the device. 5.3.
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Electrical characteristics 5.3.16 STM32F103x8, STM32F103xB Communications interfaces I2C interface characteristics The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 40.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 32. I2C bus AC waveforms and measurement circuit VDD_I2C VDD_I2C Rp Rp STM32F10x Rs SDA I²C bus Rs SCL Start repeated Start Start tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) tw(SCLL) th(SDA) tsu(STO:STA) Stop SCL tw(SCLH) tr(SCL) tsu(STO) tf(SCL) ai14133e 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 2. Rs = Series protection resistors, Rp = Pull-up resistors, VDD_I2C = I2C bus supply. Table 41.
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Electrical characteristics STM32F103x8, STM32F103xB SPI interface characteristics Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 33. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 34.
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Electrical characteristics STM32F103x8, STM32F103xB Figure 35. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed).
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STM32F103x8, STM32F103xB Electrical characteristics Table 44. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V Input levels VDD USB operating voltage(2) VDI(4) Differential input sensitivity I(USBDP, USBDM) 0.2 - VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 V Output levels VOL Static output level low RL of 1.5 k to 3.6 V(5) - 0.
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Electrical characteristics 5.3.18 STM32F103x8, STM32F103xB 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: It is recommended to perform a calibration after each power-up. Table 46. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 - 3.
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STM32F103x8, STM32F103xB Electrical characteristics Equation 1: RAIN max formula: TS R AIN  ------------------------------------------------------------- – R ADC N+2 f ADC  C ADC  ln  2  The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 47. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (k) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.
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Electrical characteristics STM32F103x8, STM32F103xB Table 49. ADC accuracy(1) (2) (3) Symbol Parameter Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 38. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL±1 µA STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14150c 1. Refer to Table 46 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
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Electrical characteristics STM32F103x8, STM32F103xB Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai14389 1. VREF+ and VREF– inputs are available only on 100-pin packages. 5.3.19 Temperature sensor characteristics Table 50. TS characteristics Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Parameter Min Typ Max Unit - 1 2 °C Average slope 4.0 4.3 4.
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STM32F103x8, STM32F103xB Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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Package characteristics STM32F103x8, STM32F103xB Figure 41. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) Figure 42. VFQFPN36 recommended footprint (dimensions in mm)(1)(2) Seating plane C ddd C 1.00 4.30 A2 A 27 19 A1 A3 E2 28 18 b 27 18 28 0.50 4.10 19 4.30 4.10 4.80 4.80 e D2 D 36 10 36 0.75 9 1 0.30 10 6.30 ai14870b Pin # 1 ID R = 0.20 1 9 L E ZR_ME 1. Drawing is not to scale. 2.
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STM32F103x8, STM32F103xB Package characteristics Figure 43. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline Pin 1 indentifier laser marking area D A E E T ddd Seating plane A1 b e Detail Y D Exposed pad area Y D2 1 L 48 C 0.500x45° pin1 corner R 0.125 typ. Detail Z E2 1 48 Z A0B9_ME_V3 1. Drawing is not to scale. 2. There is an exposed die pad on the underside of the QFPN package, this pad is not internally connected to the VSS or VDD power pads. It is recommended to connect it to VSS.
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Package characteristics STM32F103x8, STM32F103xB Table 52. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44. UFQFPN48 recommended footprint 7.30 6.20 48 37 1 36 5.60 0.20 7.30 5.80 6.20 5.60 0.30 12 25 13 0.55 84/105 24 0.50 5.
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STM32F103x8, STM32F103xB Package characteristics Figure 45. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline Z Seating plane ddd Z A4 A2 A1 A E1 e A1 ball A1 ball identifier index area F X E A F D1 D e Y K 10 1 BOTTOM VIEW Øb (100 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW H0_ME_V2 1. Drawing is not to scale. Table 53. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ A A1 Max Min Typ 1.
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Package characteristics STM32F103x8, STM32F103xB 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 46. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter – Non solder mask defined pads are recommended – 4 to 6 mils screen print Dpad Dsm .
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STM32F103x8, STM32F103xB Package characteristics Figure 47. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline(1) Figure 48. LQFP100 recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE 75 k 51 D L D1 76 50 0.5 L1 D3 51 75 C 0.3 76 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 26 Pin 1 1 identification 25 12.3 25 ccc C 16.7 e A1 ai14906 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 54.
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Package characteristics STM32F103x8, STM32F103xB Figure 49. UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 e A1 ball A1 ball identifier index area F X E A F D1 D e Y M 12 1 BOTTOM VIEW Øb (100 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW A0C2_ME_V2 1. Drawing is not to scale. Table 55. UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.
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STM32F103x8, STM32F103xB Package characteristics Figure 50. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline(1) Figure 51. LQFP64 recommended footprint(1)(2) D 48 ccc $ D1 33 48 33 " " D3 0.3 49 32 0.5 32 49 12.7 b 10.3 L1 10.3 E3 E1 E 64 L A1 17 1.2 K 1 16 64 7.8 17 Pin 1 identification 16 1 12.7 D ai14909 5W_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 56.
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Package characteristics STM32F103x8, STM32F103xB Figure 52. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline Z Seating plane ddd Z A4 A2 A1 A E1 e A1 ball A1 ball identifier index area F X E A F D1 D e Y H 8 1 BOTTOM VIEW Øb (64 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW R8_ME_V3 1. Drawing is not to scale. Table 57. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.
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STM32F103x8, STM32F103xB Package characteristics Figure 53. Recommended PCB design rules for pads (0.5 mm pitch BGA) Pitch 0.5 mm D pad 0.27 mm Dsm 0.35 mm typ (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter Dpad Dsm ai15495 1. Non solder mask defined (NSMD) pads are recommended 2.
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Package characteristics STM32F103x8, STM32F103xB Figure 54. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline(1) Figure 55. LQFP48 recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.50 1.20 0.25 mm Gage plane C D 36 37 D1 25 24 k D3 A1 L 25 36 0.20 7.30 9.70 5.80 L1 7.30 24 37 48 1 13 12 1.20 E3 E1 E 5.80 9.70 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 58.
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STM32F103x8, STM32F103xB 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 38.
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Package characteristics 6.2.2 STM32F103x8, STM32F103xB Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 60: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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STM32F103x8, STM32F103xB Package characteristics Using the values obtained in Table 59 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 60: Ordering information scheme). Figure 56. LQFP100 PD max vs.
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Ordering information scheme 7 STM32F103x8, STM32F103xB Ordering information scheme Table 60.
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STM32F103x8, STM32F103xB 8 Revision history Revision history Table 61. Document revision history Date Revision 01-jun-2007 1 Initial release. 2 Flash memory size modified in Note 9, Note 5, Note 7, Note 7 and BGA100 pins added to Table 5: Medium-density STM32F103xx pin definitions. Figure 3: STM32F103xx performance line LFBGA100 ballout added. THSE changed to TLSE in Figure 23: Low-speed external clock source AC timing diagram. VBAT ranged modified in Power supply schemes.
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Revision history STM32F103x8, STM32F103xB Table 61. Document revision history (continued) Date 18-Oct-2007 98/105 Revision Changes 3 STM32F103CBT6, STM32F103T6 and STM32F103T8 root part numbers added (see Table 2: STM32F103xx medium-density device features and peripheral counts) VFQFPN36 package added (see Section 6: Package characteristics). All packages are ECOPACK® compliant.
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STM32F103x8, STM32F103xB Revision history Table 61. Document revision history (continued) Date 22-Nov-2007 Revision Changes 4 Document status promoted from preliminary data to datasheet. The STM32F103xx is USB certified. Small text changes. Power supply schemes on page 15 modified. Number of communication peripherals corrected for STM32F103Tx and number of GPIOs corrected for LQFP package in Table 2: STM32F103xx medium-density device features and peripheral counts.
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Revision history STM32F103x8, STM32F103xB Table 61. Document revision history (continued) Date 14-Mar-2008 21-Mar-2008 22-May-2008 100/105 Revision Changes 5 Figure 2: Clock tree on page 12 added. Maximum TJ value given in Table 8: Thermal characteristics on page 38. CRC feature added (see CRC (cyclic redundancy check) calculation unit on page 9 and Figure 11: Memory map on page 34 for address). IDD modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes.
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STM32F103x8, STM32F103xB Revision history Table 61. Document revision history (continued) Date 21-Jul-2008 22-Sep-2008 Revision Changes 8 Power supply supervisor updated and VDDA added to Table 9: General operating conditions. Capacitance modified in Figure 14: Power supply scheme on page 36. Table notes revised in Section 5: Electrical characteristics. Table 16: Typical and maximum current consumptions in Stop and Standby modes modified.
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Revision history STM32F103x8, STM32F103xB Table 61. Document revision history (continued) Date 23-Apr-2009 22-Sep-2009 03-Jun-2010 102/105 Revision Changes 10 I/O information clarified on page 1. Figure 3: STM32F103xx performance line LFBGA100 ballout modified. Figure 11: Memory map modified. Table 4: Timer feature comparison added. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column in Table 5: Medium-density STM32F103xx pin definitions.
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STM32F103x8, STM32F103xB Revision history Table 61. Document revision history (continued) Date Revision Changes 19-Apr-2011 13 Updated footnotes below Table 6: Voltage characteristics on page 37 and Table 7: Current characteristics on page 38 Updated tw min in Table 20: High-speed external user clock characteristics on page 51 Updated startup time in Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 54 Added Section 5.3.12: I/O current injection characteristics Updated Section 5.3.
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Revision history STM32F103x8, STM32F103xB Table 61. Document revision history (continued) Date 14-May-2013 05-Aug-2013 104/105 Revision Changes 15 Replaced VQFN48 package with UQFN48 in cover page packages, Table 2: STM32F103xx medium-density device features and peripheral counts, Figure 9: STM32F103xx performance line UFQFPN48 pinout, Table 2: STM32F103xx medium-density device features and peripheral counts, Table 55: UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.
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STM32F103x8, STM32F103xB Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.