Datasheet
Electrical characteristics STM32F103xF, STM32F103xG
78/120 Doc ID 16554 Rev 3
NAND controller waveforms and timings
Figure 36 through Figure 39 represent synchronous waveforms and Ta ble 43 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
● COM.FSMC_SetupTime = 0x00;
● COM.FSMC_WaitSetupTime = 0x02;
● COM.FSMC_HoldSetupTime = 0x01;
● COM.FSMC_HiZSetupTime = 0x00;
● ATT.FSMC_SetupTime = 0x00;
● ATT.FSMC_WaitSetupTime = 0x02;
● ATT.FSMC_HoldSetupTime = 0x01;
● ATT.FSMC_HiZSetupTime = 0x00;
● Bank = FSMC_Bank_NAND;
● MemoryDataWidth = FSMC_MemoryDataWidth_16b;
● ECC = FSMC_ECC_Enable;
● ECCPageSize = FSMC_ECCPageSize_512Bytes;
● TCLRSetupTime = 0;
● TARSetupTime = 0;
Table 41. Switching characteristics for PC Card/CF read and write cycles in I/O space
Symbol Parameter Min Max Unit
tw
(NIOWR)
FSMC_NIOWR low width 8 THCLK - ns
tv
(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid -
5 THCLK -
4
ns
th
(NIOWR-D)
FSMC_NIOWR high to FSMC_D[15:0] invalid
11THCLK -
7
-ns
td
(NCE4_1-NIOWR)
FSMC_NCE4_1 low to FSMC_NIOWR valid -
5THCLK +
1
ns
th
(NCEx-NIOWR)
FSMC_NCEx high to FSMC_NIOWR invalid
5THCLK -
2.5
-ns
td
(NIORD-NCEx)
FSMC_NCEx low to FSMC_NIORD valid -
5THCLK -
0.5
ns
th
(NCEx-NIORD)
FSMC_NCEx high to FSMC_NIORD) valid
5 THCLK -
0.5
-ns
tw
(NIORD)
FSMC_NIORD low width 8THCLK - ns
tsu
(D-NIORD)
FSMC_D[15:0] valid before FSMC_NIORD high 28 ns
td
(NIORD-D)
FSMC_D[15:0] valid after FSMC_NIORD high 3 ns