Datasheet

Electrical characteristics STM32F103xF, STM32F103xG
64/120 Doc ID 16554 Rev 3
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
(1)
1. C
L
= 15 pF.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 3t
HCLK
+ 0.5 3t
HCLK
+ 1.5 ns
t
v(NWE_NE)
FSMC_NEx low to FSMC_NWE low t
HCLK
+ 0.5 t
HCLK
+ 1.5 ns
t
w(NWE)
FSMC_NWE low time t
HCLK
– 0.5 t
HCLK
+ 1 ns
t
h(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time t
HCLK
– 0.5 - ns
t
v(A_NE)
FSMC_NEx low to FSMC_A valid - 0 ns
t
h(A_NWE)
Address hold time after FSMC_NWE high t
HCLK
-ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 1.5 ns
t
h(BL_NWE)
FSMC_BL hold time after FSMC_NWE high t
HCLK
– 1.5 - ns
t
v(Data_NE)
FSMC_NEx low to Data valid - t
HCLK
ns
t
h(Data_NWE)
Data hold time after FSMC_NWE high t
HCLK
-ns
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low - 0 ns
t
w(NADV)
FSMC_NADV low time - t
HCLK
+ 1.5 ns
Table 33. Asynchronous read muxed
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 7t
HCLK
+ 0.5 7t
HCLK
+ 2
ns
t
v(NOE_NE)
FSMC_NEx low to FSMC_NOE low 3t
HCLK
+ 0.5 3t
HCLK
+ 1.5
t
w(NOE)
FSMC_NOE low time 4t
HCLK
– 1 4t
HCLK
+ 1
t
h(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time 0.5 -
t
v(A_NE)
FSMC_NEx low to FSMC_A valid - 0
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 0 1
t
w(NADV)
FSMC_NADV low time t
HCLK
+ 0.5 t
HCLK
+ 2
t
h(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC NADV high
t
HCLK
-
t
h(A_NOE)
Address hold time after FSMC_NOE high t
HCLK
– 2 -
t
h(BL_NOE)
FSMC_BL time after FSMC_NOE high 0.5 -
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 0
t
su(Data_NE)
Data to FSMC_NEx high setup time 4t
HCLK
– 0.5 -
t
su(Data_NOE)
Data to FSMC_NOE high setup time 4t
HCLK
– 1 -
t
h(Data_NE)
Data hold time after FSMC_NEx high 0 -
t
h(Data_NOE)
Data hold time after FSMC_NOE high 0 -