Datasheet

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Doc ID 14611 Rev 8 91/130
Figure 46. I/O AC characteristics definition
5.3.15 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see Ta ble 46).
Unless otherwise specified, the parameters given in Ta ble 49 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Tabl e 1 0 .
Figure 47. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 49. Otherwise the reset will not be taken into account by the device.
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10%
90%
50%
t
r(IO)out
OUTPUT
EXT ERNAL
ON 50pF
Maximum frequency is achieved if (t
r
+ t
f
) ≤ 2/3)T and if the duty cycle is (45-55%)
10 %
50%
90%
when loaded by 50pF
T
t
r(IO)out
Table 49. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL(NRST)
(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage –0.5 0.8
V
V
IH(NRST)
(1)
NRST Input high level voltage 2 V
DD
+0.5
V
hys(NRST)
NRST Schmitt trigger voltage
hysteresis
200 mV
R
PU
Weak pull-up equivalent resistor
(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
V
IN
= V
SS
30 40 50 kΩ
V
F(NRST)
(1)
NRST Input filtered pulse 100 ns
V
NF(NRST)
(1)
NRST Input not filtered pulse 300 ns
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STM32F10xxx
R
PU
NRST
(2)
V
DD
Filter
Internal Reset
0.1 µF
External
reset circuit
(1)