Datasheet

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Doc ID 14611 Rev 8 89/130
Output voltage levels
Unless otherwise specified, the parameters given in Ta ble 47 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Tabl e 1 0 . All I/Os are CMOS and TTL compliant.
Table 47. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
V
OL
(1)
1. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
CMOS port
(2)
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
0.4
V
V
OH
(3)
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD
.
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
–0.4
V
OL
(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
TTL port
(2)
I
IO
=+ 8mA
2.7 V < V
DD
< 3.6 V
0.4
V
V
OH
(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
2.4
V
OL
(1)(4)
4. Based on characterization data, not tested in production.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
I
IO
= +20 mA
2.7 V < V
DD
< 3.6 V
1.3
V
V
OH
(3)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
–1.3
V
OL
(1)(4)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
I
IO
= +6 mA
2 V < V
DD
< 2.7 V
0.4
V
V
OH
(3)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
V
DD
–0.4