Datasheet

Electrical characteristics STM32F103x4, STM32F103x6
64/90 Doc ID 15060 Rev 6
5.3.16 Communications interfaces
I
2
C interface characteristics
The STM32F103xx performance line
I
2
C interface meets the requirements of the standard
I
2
C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in Ta bl e 4 0 . Refer also to Section 5.3.12: I/O current
injection characteristics
for more details on the input/output alternate function characteristics
(SDA and SCL)
.
Table 40. I
2
C characteristics
Symbol Parameter
Standard mode I
2
C
(1)
1.
Guaranteed by design, not tested in production.
Fast mode I
2
C
(1)(2)
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I
2
C frequencies. It must be at least 4 MHz to
achieve fast mode I
2
C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C
fast mode clock.
Unit
Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 1.3
µs
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100
ns
t
h(SDA)
SDA data hold time 0 0 900
(3)
3.
The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
t
r(SDA)
t
r(SCL)
SDA and SCL rise time 1000 20 + 0.1C
b
300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300 300
t
h(STA)
Start condition hold time 4.0 0.6
µs
t
su(STA)
Repeated Start condition
setup time
4.7 0.6
t
su(STO)
Stop condition setup time 4.0 0.6 μs
t
w(STO:STA)
Stop to Start condition time
(bus free)
4.7 1.3 μs
C
b
Capacitive load for each bus
line
400 400 pF