Datasheet

STM32F103x4, STM32F103x6 Pinouts and pin description
Doc ID 15060 Rev 6 27/90
- - C1 2 PD0 I/O FT PD0
- - D1 3 PD1 I/O FT PD1
54 B5 - PD2 I/O FT PD2 TIM3_ETR
39 55 A5 30 PB3 I/O FT JTDO
TIM2_CH2 / PB3/
TRACESWO
SPI1_SCK
40 56 A4 31 PB4 I/O FT NJTRST
TIM3_CH1 /PB4
SPI1_MISO
41 57 C4 32 PB5 I/O PB5 I2C1_SMBA
TIM3_CH2 /
SPI1_MOSI
42 58 D3 33 PB6 I/O FT PB6 I2C1_SCL
(9)
/ USART1_TX
43 59 C3 34 PB7 I/O FT PB7 I2C1_SDA
(9)
USART1_RX
44 60 B4 35 BOOT0 I BOOT0
45 61 B3 - PB8 I/O FT PB8
I2C1_SCL
/CAN_RX
46 62 A3 - PB9 I/O FT PB9
I2C1_SDA /
CAN_TX
47 63 D4 36 V
SS_3
SV
SS_3
48 64 E4 1 V
DD_3
SV
DD_3
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 10.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48, UFQFPN48 and LQFP64 packages and C1
and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and
PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug
configuration section in the STM32F10xxx reference manual.
8. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V
REF+
functionality is provided instead.
9. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
Table 5. Low-density STM32F103xx pin definitions (continued)
Pins
Pin name
Type
(1)
I / O Level
(2)
Main
function
(3)
(after reset)
Alternate functions
(4)
LQFP48/
UFQFPN48
LQFP64
TFBGA64
VFQFPN36
Default Remap