Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 72 MHz I/O number 51

This is information on a product in full production.

May 2013 Doc ID 15060 Rev 6 1/90

STM32F103x4

STM32F103x6

Low-density performance line, ARM-based 32-bit MCU with 16 or

32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 com. interfaces

Datasheet − production data

Features

■ ARM 32-bit Cortex™-M3 CPU Core

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

■ Memories

– 16 or 32 Kbytes of Flash memory

– 6 or 10 Kbytes of SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

■ 2 x 12-bit, 1 µs A/D converters (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Dual-sample and hold capability

– Temperature sensor

■ DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

Cs and USARTs

■ Up to 51 fast I/O ports

– 26/37/51 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

■ 6 timers

– Two 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– 16-bit, motor control PWM timer with dead-

time generation and emergency stop

– 2 watchdog timers (Independent and

Window)

– SysTick timer 24-bit downcounter

■ 6 communication interfaces

– 1 x I

C interface (SMBus/PMBus)

– 2 × USARTs (ISO 7816 interface, LIN, IrDA

capability, modem control)

– 1 × SPI (18 Mbit/s)

– CAN interface (2.0B Active)

– USB 2.0 full-speed interface

■ CRC calculation unit, 96-bit unique ID

■ Packages are ECOPACK

Table 1. Device summary

Reference Part number

STM32F103x4

STM32F103C4, STM32F103R4,

STM32F103T4

STM32F103x6

STM32F103C6, STM32F103R6,

STM32F103T6

LQFP64 (10 × 10 mm)

LQFP48 (7 × 7 mm)

TFBGA64 (5 × 5 mm)

VFQFPN36 (6 × 6 mm)UFQFPN48 (7 × 7 mm)

www.st.com

Summary of content (90 pages)

PAGE 1
STM32F103x4 STM32F103x6 Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 com. interfaces Datasheet − production data Features ■ ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division ■ Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of SRAM ■ Clock, reset and supply management – 2.0 to 3.
PAGE 2
Contents STM32F103x4, STM32F103x6 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Overview . . . .
PAGE 3
STM32F103x4, STM32F103x6 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 6 Contents Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.3 Typical curves . . . . . . . . . . .
PAGE 4
Contents STM32F103x4, STM32F103x6 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
STM32F103x4, STM32F103x6 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . .
PAGE 6
List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. 6/90 STM32F103x4, STM32F103x6 USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
STM32F103x4, STM32F103x6 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
PAGE 8
List of figures Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 8/90 STM32F103x4, STM32F103x6 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 80 Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 81 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . .
PAGE 9
STM32F103x4, STM32F103x6 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x4 and STM32F103x6 low-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The low-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual.
PAGE 10
Description 2.1 STM32F103x4, STM32F103x6 Device overview Table 2.
PAGE 11
STM32F103x4, STM32F103x6 STM32F103xx performance line block diagram TPIU Trace Controlle r pbu s Trace/trig SW/JTAG Ibus Cortex-M3 CPU Fmax : 7 2M Hz Dbus Syst em NVIC AHB:F max =48/72 MHz @VDDA SUPPLY SUPERVISION NRST VDDA VSSA Rst PVD Int @VDD PLL & CLOCK MANAGT XTAL OSC 4-16 MHz AHB2 APB2 GPIOA GPIOB PC[15:0] GPIOC PD[2:0] GPIOD 4 Chann els 3 co mpl.
PAGE 12
Description STM32F103x4, STM32F103x6 Figure 2. Clock tree 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz HCLK to AHB bus, core, memory and DMA 72 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..
PAGE 13
STM32F103x4, STM32F103x6 2.2 Description Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.
PAGE 14
Description STM32F103x4, STM32F103x6 2.3 Overview 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
PAGE 15
STM32F103x4, STM32F103x6 Description This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests.
PAGE 16
Description STM32F103x4, STM32F103x6 in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold.
PAGE 17
STM32F103x4, STM32F103x6 2.3.13 Description DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel.
PAGE 18
Description STM32F103x4, STM32F103x6 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer.
PAGE 19
STM32F103x4, STM32F103x6 Description SysTick timer This timer is dedicated for OS, but could also be used as a standard downcounter. It features: 2.3.16 ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ● Programmable clock source I²C bus The I²C bus interface can operate in multimaster and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
PAGE 20
Description 2.3.21 STM32F103x4, STM32F103x6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.
PAGE 21
STM32F103x4, STM32F103x6 Pinouts and pin description STM32F103xx performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 3.
PAGE 22
Pinouts and pin description Figure 4.
PAGE 23
STM32F103x4, STM32F103x6 STM32F103xx performance line LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 5.
PAGE 24
Pinouts and pin description PB7 PB6 PB5 PB4 PB3 PA15 PA14 36 BOOT0 STM32F103xx performance line VFQFPN36 pinout VSS_3 Figure 7.
PAGE 25
STM32F103x4, STM32F103x6 Low-density STM32F103xx pin definitions VFQFPN36 Main function(3) (after reset) TFBGA64 Type(1) Alternate functions(4) LQFP64 LQFP48/ UFQFPN48 Pins I / O Level(2) Table 5.
PAGE 26
Pinouts and pin description Low-density STM32F103xx pin definitions (continued) 25 H6 18 26 F5 15 Pin name Type(1) TFBGA64 - VFQFPN36 LQFP64 LQFP48/ UFQFPN48 Pins I / O Level(2) Table 5.
PAGE 27
STM32F103x4, STM32F103x6 Low-density STM32F103xx pin definitions (continued) VFQFPN36 Main function(3) (after reset) TFBGA64 Type(1) Alternate functions(4) LQFP64 LQFP48/ UFQFPN48 Pins I / O Level(2) Table 5.
PAGE 28
Memory mapping 4 STM32F103x4, STM32F103x6 Memory mapping The memory map is shown in Figure 8. Figure 8.
PAGE 29
STM32F103x4, STM32F103x6 Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 30
Electrical characteristics Figure 9. STM32F103x4, STM32F103x6 Pin loading conditions Figure 10. Pin input voltage STM32F103xx pin STM32F103xx pin C = 50 pF VIN ai14141 5.1.6 ai14142 Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 × 100 nF + 1 × 4.
PAGE 31
STM32F103x4, STM32F103x6 5.1.7 Electrical characteristics Current consumption measurement Figure 12. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device.
PAGE 32
Electrical characteristics Table 7. STM32F103x4, STM32F103x6 Current characteristics Symbol Ratings Max.
PAGE 33
STM32F103x4, STM32F103x6 Table 9. Symbol Electrical characteristics General operating conditions (continued) Parameter Conditions Min Max –0.3 VDD+ 0.3 2 V < VDD ≤ 3.6 V –0.3 5.5 VDD = 2 V –0.3 5.2 0 5.
PAGE 34
Electrical characteristics Table 11. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst STM32F103x4, STM32F103x6 (2) VPOR/PDR VPDRhyst (2) Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.
PAGE 35
STM32F103x4, STM32F103x6 5.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.24 V 5.1 17.
PAGE 36
Electrical characteristics Table 13.
PAGE 37
STM32F103x4, STM32F103x6 Electrical characteristics Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 45 40 Consumption (mA) 35 30 72 MHz 25 36 MHz 16 MHz 20 8 MHz 15 10 5 0 – 45°C 25 °C 70 °C 85 °C 105 °C Temperature (°C) Figure 14. Typical current consumption in Run mode versus frequency (at 3.
PAGE 38
Electrical characteristics Table 15. STM32F103x4, STM32F103x6 Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 26 27 48 MHz 17 18 36 MHz 14 15 24 MHz 10 11 16 MHz 7 8 8 MHz 4 5 72 MHz 7.5 8 48 MHz 6 6.5 36 MHz 5 5.5 24 MHz 4.5 5 16 MHz 4 4.
PAGE 39
STM32F103x4, STM32F103x6 Table 16. Electrical characteristics Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2.0 V = 2.4 V = 3.
PAGE 40
Electrical characteristics STM32F103x4, STM32F103x6 Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V 120 Consumption (µA) 100 80 3.3 V 60 3.6 V 40 20 0 –45 °C 25 °C 85 °C 105 °C Temperature (°C) Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 90 80 Consumption (µA) 70 60 50 3.3 V 3.
PAGE 41
STM32F103x4, STM32F103x6 Electrical characteristics Figure 18. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 4.5 4 Consumption (µA) 3.5 3 2.5 3.3 V 2 3.6 V 1.5 1 0.5 0 –45 °C 25 °C 85 °C 105 °C Temperature (°C) Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load). ● All peripherals are disabled except if it is explicitly mentioned.
PAGE 42
Electrical characteristics Table 17. STM32F103x4, STM32F103x6 Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals disabled enabled(2) 72 MHz 31.3 24.5 48 MHz 21.9 17.4 36 MHz 17.2 13.8 24 MHz 11.2 8.9 16 MHz 8.1 6.6 8 MHz 5 4.2 4 MHz 3 2.
PAGE 43
STM32F103x4, STM32F103x6 Table 18. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions Supply current in Sleep mode All peripherals All peripherals enabled(2) disabled 72 MHz 12.6 5.3 48 MHz 8.7 3.8 36 MHz 6.7 3.1 24 MHz 4.8 2.3 16 MHz 3.4 1.8 8 MHz 2 1.2 4 MHz 1.5 1.1 2 MHz 1.25 1 1 MHz 1.1 0.98 500 kHz 1.05 0.96 125 kHz 1 0.95 64 MHz 10.6 4.2 48 MHz 8.1 3.2 36 MHz 6.1 2.
PAGE 44
Electrical characteristics STM32F103x4, STM32F103x6 On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19.
PAGE 45
STM32F103x4, STM32F103x6 Table 20. Electrical characteristics High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 25 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.
PAGE 46
Electrical characteristics STM32F103x4, STM32F103x6 Figure 19. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Figure 20.
PAGE 47
STM32F103x4, STM32F103x6 Table 22. Symbol Electrical characteristics HSE 4-16 MHz oscillator characteristics(1) (2) Parameter fOSC_IN Conditions Typ Max Unit 4 8 16 MHz Oscillator frequency RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) i2 HSE driving current (4) 200 kΩ 30 pF RS = 30 Ω VDD = 3.
PAGE 48
Electrical characteristics Table 23. Symbol STM32F103x4, STM32F103x6 LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2) Parameter Conditions Min Typ Max Unit RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS) RS = 30 KΩ 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS 1.4 µA gm Oscillator transconductance tSU(LSE)(3) 5 5 VDD is stabilized Startup time MΩ µA/V TA = 50 °C 1.5 TA = 25 °C 2.
PAGE 49
STM32F103x4, STM32F103x6 Electrical characteristics Figure 22. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator Bias controlled gain RF STM32F103xx OSC32_OU T CL2 ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 24.
PAGE 50
Electrical characteristics STM32F103x4, STM32F103x6 Low-speed internal (LSI) RC oscillator Table 25. LSI oscillator characteristics (1) Symbol fLSI(2) Parameter Frequency tsu(LSI)(3) LSI oscillator startup time IDD(LSI)(3) LSI oscillator power consumption Min Typ Max Unit 30 40 60 kHz 85 µs 1.2 µA 0.65 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
PAGE 51
STM32F103x4, STM32F103x6 Table 26. Electrical characteristics Low-power mode wakeup timings Symbol Parameter tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Typ Unit Wakeup from Sleep mode 1.8 µs Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low power mode) 5.4 Wakeup from Standby mode 50 µs µs 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 5.3.
PAGE 52
Electrical characteristics Table 28. Symbol IDD Vprog STM32F103x4, STM32F103x6 Flash memory characteristics (continued) Max(1) Unit Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V 20 mA Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 µA 3.6 V Parameter Supply current Conditions Programming voltage Min(1) Typ 2 1. Guaranteed by design, not tested in production. Table 29.
PAGE 53
STM32F103x4, STM32F103x6 Table 30. Electrical characteristics EMS characteristics Symbol Parameter Level/ Class Conditions VFESD VDD = 3.3 V, TA = +25 °C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.
PAGE 54
Electrical characteristics 5.3.11 STM32F103x4, STM32F103x6 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
PAGE 55
STM32F103x4, STM32F103x6 5.3.12 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
PAGE 56
Electrical characteristics 5.3.13 STM32F103x4, STM32F103x6 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35.
PAGE 57
STM32F103x4, STM32F103x6 Electrical characteristics 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
PAGE 58
Electrical characteristics STM32F103x4, STM32F103x6 All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and in Figure 25 and Figure 26 for 5 V tolerant I/Os. Figure 23.
PAGE 59
STM32F103x4, STM32F103x6 Electrical characteristics Figure 25. 5 V tolerant I/O input characteristics - CMOS port !REA NOT DETERMINED 6)( 6), 6 6 $$ NTS 6 )( QUIREME DARD RE /3 STAN #- IN 4ESTED ON PRODUCTI 6 )( 6 $$ SIMULATIONS GN SI DE ON D "ASE 6 ), 6 $$ IONS SIGN SIMULAT "ASED ON DE 6 $$ ENT 6 ), DARD REQUIRM #-/3 STAN ODUCTION 4ESTED IN PR 6$$ 6 6$$ AI C Figure 26.
PAGE 60
Electrical characteristics STM32F103x4, STM32F103x6 Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
PAGE 61
STM32F103x4, STM32F103x6 Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 27 and Table 37, respectively. Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37.
PAGE 62
Electrical characteristics STM32F103x4, STM32F103x6 Figure 27. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% External Output on 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50 pF ai14131 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 35).
PAGE 63
STM32F103x4, STM32F103x6 Electrical characteristics Figure 28. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal reset Filter 0.1 µF STM32F10x ai14132d 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 38. Otherwise the reset will not be taken into account by the device. 5.3.
PAGE 64
Electrical characteristics 5.3.16 STM32F103x4, STM32F103x6 Communications interfaces I2C interface characteristics The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 40.
PAGE 65
STM32F103x4, STM32F103x6 Electrical characteristics Figure 29. I2C bus AC waveforms and measurement circuit 6$$?) # 6$$?) # Rp Rp 34- & X Rs 3$! )£# BUS Rs 3#, 3TART REPEATED 3TART 3TART TSU 34! 3$! TF 3$! TR 3$! TH 34! TSU 3$! TW 3#,, TH 3$! TSU 34/ 34! 3TOP 3#, TW 3#,( TR 3#, TSU 34/ TF 3#, AI E 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 2. Rs = Series protection resistors, Rp = Pull-up resistors, VDD_I2C = I2C bus supply. Table 41.
PAGE 66
Electrical characteristics STM32F103x4, STM32F103x6 SPI interface characteristics Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42.
PAGE 67
STM32F103x4, STM32F103x6 Electrical characteristics Figure 30. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 31.
PAGE 68
Electrical characteristics STM32F103x4, STM32F103x6 Figure 32. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed).
PAGE 69
STM32F103x4, STM32F103x6 Table 44. Electrical characteristics USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V V Input levels VDD USB operating voltage(2) VDI(4) Differential input sensitivity I(USBDP, USBDM) 0.2 VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 Output levels VOL Static output level low RL of 1.5 kΩ to 3.
PAGE 70
Electrical characteristics 5.3.18 STM32F103x4, STM32F103x6 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: It is recommended to perform a calibration after each power-up. Table 46. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Power supply 2.4 3.
PAGE 71
STM32F103x4, STM32F103x6 Electrical characteristics Equation 1: RAIN max formula: TS R AIN < --------------------------------------------------------------- – R ADC N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 47. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.
PAGE 72
Electrical characteristics STM32F103x4, STM32F103x6 ADC accuracy(1) (2) (3) Table 49. Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
PAGE 73
STM32F103x4, STM32F103x6 Electrical characteristics Figure 35. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL±1 µA STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14150c 1. Refer to Table 46 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
PAGE 74
Electrical characteristics STM32F103x4, STM32F103x6 Figure 37. Power supply and reference decoupling(VREF+ connected to VDDA) 34- & X 6$$! 62%& SEE NOTE & N& 633! AI 1. The VREF+ input is available only on the TFBGA64 package. 5.3.19 Temperature sensor characteristics Table 50. TS characteristics Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Parameter Min VSENSE linearity with temperature Typ Max Unit ±1 ±2 °C Average slope 4.0 4.3 4.
PAGE 75
STM32F103x4, STM32F103x6 Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
PAGE 76
Package characteristics STM32F103x4, STM32F103x6 Figure 38. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) Figure 39. Recommended footprint (dimensions in mm)(1)(2) Seating plane C ddd C 1.00 4.30 A2 A 27 19 A1 A3 E2 28 18 b 27 18 28 0.50 4.10 19 4.30 4.10 4.80 4.80 e D2 D 36 10 9 1 36 0.75 0.30 10 6.30 ai14870b Pin # 1 ID R = 0.20 1 9 L E ZR_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.
PAGE 77
STM32F103x4, STM32F103x6 Package characteristics Figure 40. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline 0IN INDENTIFIER LASER MARKING AREA $ ! % % 4 DDD ! 3EATING PLANE B E $ETAIL 9 $ %XPOSED PAD AREA 9 $ , # X PIN CORNER 2 TYP $ETAIL : % : ! " ?-%?6 1. Drawing is not to scale. 2. There is an exposed die pad on the underside of the QFPN package, this pad is not internally connected to the VSS or VDD power pads. It is recommended to connect it to VSS. 3.
PAGE 78
Package characteristics STM32F103x4, STM32F103x6 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 41.
PAGE 79
STM32F103x4, STM32F103x6 Package characteristics Figure 42. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline(1) Figure 43. Recommended footprint(1)(2) $ 48 CCC $ $ 33 " " $ 0.3 49 32 0.5 12.7 B 10.3 , 10.3 % % % 64 , ! 0IN IDENTIFICATION 17 1.2 + 1 16 7.8 12.7 D ai14909 7?-% 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 53.
PAGE 80
Package characteristics STM32F103x4, STM32F103x6 Figure 44. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline Z Seating plane ddd Z A4 A2 A1 A E1 e A1 ball A1 ball identifier index area F X E A F D1 D e Y H 8 1 BOTTOM VIEW Øb (64 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW R8_ME_V3 1. Drawing is not to scale. Table 54. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ A A1 Max Min 1.200 0.
PAGE 81
STM32F103x4, STM32F103x6 Package characteristics Figure 45. Recommended PCB design rules for pads (0.5 mm pitch BGA) Pitch 0.5 mm D pad 0.27 mm Dsm 0.35 mm typ (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter Dpad Dsm ai15495 1. Non solder mask defined (NSMD) pads are recommended 2.
PAGE 82
Package characteristics STM32F103x4, STM32F103x6 Figure 46. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline(1) Figure 47. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.25 mm Gage plane C D D1 k D3 A1 L 25 36 24 37 L1 E3 E1 E 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 55.
PAGE 83
STM32F103x4, STM32F103x6 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 32.
PAGE 84
Package characteristics 6.2.2 STM32F103x4, STM32F103x6 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 57: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
PAGE 85
STM32F103x4, STM32F103x6 Package characteristics Using the values obtained in Table 56 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 115 °C + (45 °C/W × 134 mW) = 115 °C + 6.03 °C = 121.03 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 57: Ordering information scheme). Figure 48. LQFP64 PD max vs.
PAGE 86
Ordering information scheme 7 STM32F103x4, STM32F103x6 Ordering information scheme Table 57.
PAGE 87
STM32F103x4, STM32F103x6 8 Revision history Revision history Table 58. Document revision history Date Revision 22-Sep-2008 1 Initial release. 2 “96-bit unique ID” feature added and I/O information clarified on page 1. Timers specified on page 1 (Motor control capability mentioned). Table 4: Timer feature comparison added. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, plus small additional changes in Table 5: Low-density STM32F103xx pin definitions.
PAGE 88
Revision history Table 58. STM32F103x4, STM32F103x6 Document revision history (continued) Date 24-Sep-2009 20-May-2010 19-Apr-2011 88/90 Revision Changes 3 Note 5 updated and Note 4 added in Table 5: Low-density STM32F103xx pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. Typical IDD_VBAT value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes.
PAGE 89
STM32F103x4, STM32F103x6 Table 58.
PAGE 90
STM32F103x4, STM32F103x6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.