Datasheet

Electrical characteristics STM32F102x8, STM32F102xB
66/80 DocID15056 Rev 5
Equation 1: R
AIN
max formula:
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 45. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
DDA
Power supply 2.4 3.6 V
f
ADC
ADC clock frequency 0.6 12 MHz
f
S
(1)
1. Guaranteed by design, not tested in production.
Sampling rate 0.05 0.85 Msps
f
TRIG
(1)
External trigger frequency
f
ADC
= 12 MHz 823 kHz
17 1/f
ADC
V
AIN
Conversion voltage range
(2)
2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA,
0 (V
SSA
or
V
REF-
tied to
ground)
V
REF+
V
R
AIN
(1)
External input impedance
See Equation 1
and Table 48
for details
50 κΩ
R
ADC
(1)
Sampling switch resistance 1 κΩ
C
ADC
(1)
Internal sample and hold
capacitor
8pF
t
CAL
(1)
Calibration time
f
ADC
= 12 MHz 5.9 µs
83 1/f
ADC
t
lat
(1)
Injection trigger conversion
latency
f
ADC
= 12 MHz 0.214 µs
3
(3)
3. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in Table 47.
1/f
ADC
t
latr
(1)
Regular trigger conversion
latency
f
ADC
= 12 MHz 0.143 µs
2
(3)
1/f
ADC
t
S
(1)
Sampling time
f
ADC
= 12 MHz 0.125 19.95 µs
1.5 239.5 1/f
ADC
t
STAB
(1)
Power-up time 0 0 1 µs
t
CONV
(1)
Total conversion time
(including sampling time)
f
ADC
= 12 MHz 1.2 21 µs
14 to 252 (t
S
for sampling +12.5
for successive approximation)
1/f
ADC
R
AIN
T
S
f
ADC
C
ADC
2
N2+
()ln××
------------------------------------------------------------- R
ADC
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