Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 32-Bit 48 MHz I/O number 37

Pinout and pin description STM32F102x8, STM32F102xB

22/80 DocID15056 Rev 5

38 50 PA15 I/O FT JTDI

TIM2_CH1_ETR

/ PA15

/SPI1_NSS

- 51 PC10 I/O FT PC10 USART3_TX

- 52 PC11 I/O FT PC11 USART3_RX

- 53 PC12 I/O FT PC12 USART3_CK

- 54 PD2 I/O FT PD2 TIM3_ETR

39 55 PB3 I/O FT JTDO

TIM2_CH2/ PB3/

TRACESWO/

SPI1_SCK

40 56 PB4 I/O FT JNTRST

TIM3_CH1 / PB4

SPI1_MISO

41 57 PB5 I/O PB5 I2C1_SMBA

TIM3_CH2 /

SPI1_MOSI

42 58 PB6 I/O FT PB6 I2C1_SCL

(8)

/ TIM4_CH1 USART1_TX

43 59 PB7 I/O FT PB7 I2C1_SDA

(8)

/ TIM4_CH2 USART1_RX

44 60 BOOT0 I BOOT0

45 61 PB8 I/O FT PB8 TIM4_CH3 I2C1_SCL

46 62 PB9 I/O FT PB9 TIM4_CH4 I2C1_SDA

47 63 V

SS_3

48 64 V

DD_3

1. I = input, O = output, S = supply.

2. FT= 5 V tolerant.

3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower

number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be

called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 9Table 3 on page 12.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should

be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3

mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load

of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even

after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from the

STMicroelectronics website: www.st.com.

Table 4. Medium-density STM32F102xx pin definitions (continued)

Pins

Pin name

Type

(1)

I / O level

(2)

Main

function

(3)

(after reset)

Alternate functions

(3)

(4)

LQFP48

LQFP64

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