Datasheet

Electrical characteristics STM32F101xF, STM32F101xG
96/108 Doc ID 17143 Rev 2
Figure 50. Typical connection diagram using the ADC
1. Refer to Table 55 for the values of R
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 51 or Figure 52,
depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 51. Power supply and reference decoupling (V
REF+
not connected to V
DDA
)
1. V
REF+
and V
REF-
inputs are available only on 100-pin packages.
ai14139d
STM32F10xxx
V
DD
AINx
I
L
±1 µA
0.6 V
V
T
R
AIN
(1)
C
parasitic
V
AIN
0.6 V
V
T
R
ADC
(1)
C
ADC
(1)
12-bit
converter
Sample and hold ADC
converter
V
REF+
STM32F10xxx
V
DDA
V
SSA
/V
REF-
1 µF // 10 nF
1 µF // 10 nF
ai14380b