Datasheet

Electrical characteristics STM32F101xF, STM32F101xG
90/108 Doc ID 17143 Rev 2
Table 54. SPI characteristics
(1)
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode 18
MHz
Slave mode 18
t
r(SCK)
t
f(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF 8 ns
DuCy(SCK)
SPI slave input clock duty
cycle
Slave mode 30 70 %
t
su(NSS)
(2)
NSS setup time Slave mode 4t
PCLK
ns
t
h(NSS)
(2)
NSS hold time Slave mode 2t
PCLK
t
w(SCKH)
(2)
t
w(SCKL)
(2)
SCK high and low time
Master mode, f
PCLK
= 36 MHz,
presc = 4
50 60
t
su(MI)
(2)
t
su(SI)
(2)
Data input setup time
Master mode 5
Slave mode 5
t
h(MI)
(2)
Data input hold time
Master mode 5
t
h(SI)
(2)
Slave mode 4
t
a(SO)
(2)(3)
Data output access time Slave mode, f
PCLK
= 20 MHz 0 3t
PCLK
t
dis(SO)
(2)(4)
Data output disable time Slave mode 2 10
t
v(SO)
(2)(1)
Data output valid time Slave mode (after enable edge) 25
t
v(MO)
(2)(1)
Data output valid time Master mode (after enable edge) 5
t
h(SO)
(2)
Data output hold time
Slave mode (after enable edge) 15
t
h(MO)
(2)
Master mode (after enable edge) 2
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z