Datasheet

STM32F101xF, STM32F101xG Electrical characteristics
Doc ID 17143 Rev 2 89/108
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 53Table 54 are derived from tests
performed under ambient temperature, f
PCLKx
frequency and V
DD
supply voltage conditions
summarized in Table 10 .
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 53. STM32F10xxx SPI characteristics
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode 10
MHz
Slave mode 10
t
r(SCK)
t
f(SCK)
SPI clock rise and
fall time
Capacitive load: C = 30 pF 8
ns
t
su(NSS)
(1)
1. Based on characterization, not tested in production.
NSS setup time Slave mode 4t
PCLK
t
h(NSS)
(1)
NSS hold time Slave mode 73
t
w(SCKH)
(1)
t
w(SCKL)
(1)
SCK high and low
time
Master mode, f
PCLK
= 36 MHz,
presc = 4
50 60
t
su(MI)
(1)
t
su(SI)
(1)
Data input setup
time
Master mode - SPI1 3
Master mode - SPI2 5
Slave mode 4
t
h(MI)
(1)
Data input hold time
Master mode - SPI1 4
Master mode - SPI2 6
t
h(SI)
(1)
Slave mode 5
t
a(SO)
(1)(2)
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access
time
Slave mode, f
PCLK
= 36 MHz,
presc = 4
055
Slave mode, f
PCLK
= 20 MHz 4t
PCLK
t
dis(SO)
(1)(3)
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable
time
Slave mode 10
t
v(SO)
(1)
Data output valid
time
Slave mode (after enable edge) 25
t
v(MO)
(1)
Data output valid
time
Master mode (after enable edge) 6
t
h(SO)
(1)
Data output hold
time
Slave mode (after enable edge) 25
t
h(MO)
(1)
Master mode (after enable edge) 6