Datasheet

Electrical characteristics STM32F101xF, STM32F101xG
86/108 Doc ID 17143 Rev 2
5.3.16 TIM timer characteristics
The parameters given in Ta ble 5 0 are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
5.3.17 Communications interfaces
I
2
C interface characteristics
Unless otherwise specified, the parameters given in Ta ble 5 1 are derived from tests
performed under ambient temperature, f
PCLK1
frequency and V
DD
supply voltage conditions
summarized in Table 10 .
The STM32F101xC, STM32F101xD and STM32F101xESTM32F101xF and STM32F101xG
access line I
2
C interface meets the requirements of the standard I
2
C communication
protocol with the following restrictions: t
he I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in Ta bl e 5 1 . Refer also to
Section 5.3.14: I/O port
characteristics
for more details on the input/output alternate function characteristics (SDA
and SCL)
.
Table 50. TIMx
(1)
characteristics
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
Symbol Parameter Conditions Min Max Unit
t
res(TIM)
Timer resolution time
1
t
TIMxCLK
f
TIMxCLK
= 36 MHz
27.8 ns
f
EXT
Timer external clock
frequency on CH1 to CH4
0
f
TIMxCLK
/2
MHz
f
TIMxCLK
= 36 MHz
018MHz
Res
TIM
Timer resolution 16 bit
t
COUNTER
16-bit counter clock period
when internal clock is
selected
1 65536
t
TIMxCLK
f
TIMxCLK
= 36 MHz
0.0278 1820 µs
t
MAX_COUNT
Maximum possible count
65536 × 65536
t
TIMxCLK
f
TIMxCLK
= 36 MHz
119.2 s