Datasheet

Electrical characteristics STM32F101xF, STM32F101xG
68/108 Doc ID 17143 Rev 2
Figure 28. Synchronous non-multiplexed PSRAM write timings
Table 38. Synchronous non-multiplexed PSRAM write timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 27.7 ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2) 2 ns
t
d(CLKH-NExH)
FSMC_CLK high to FSMC_NEx high (x = 0...2) T
HCLK
+ 2 ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low 4 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 5 ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
t
d(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25) T
CK
+ 2 ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low 1 ns
t
d(CLKH-NWEH)
FSMC_CLK high to FSMC_NWE high T
HCLK
+ 1 ns
t
d(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low 6 ns
t
su(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high 7 ns
t
h(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high 2 ns
t
d(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high 1 ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NWE
FSMC_D[15:0]
D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 1
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKH-NExH)
t
d(CLKL-AV)
t
d(CLKH-AIV)
t
d(CLKH-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14993e
FSMC_NADV
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
d(CLKL-Data)
FSMC_NBL
t
d(CLKL-NBLH)