Datasheet

STM32F101xF, STM32F101xG Electrical characteristics
Doc ID 17143 Rev 2 67/108
Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings
Table 37. Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 27.7 ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns
t
d(CLKH-NExH)
FSMC_CLK high to FSMC_NEx high (x = 0...2) T
HCLK
+ 2 ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low 4 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 5 ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 0...25) 0 ns
t
d(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x = 0...25) T
HCLK
+ 4 ns
t
d(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low T
HCLK
+ 1.5 ns
t
d(CLKH-NOEH)
FSMC_CLK high to FSMC_NOE high T
HCLK
+ 1.5 ns
t
su(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK high 6.5 ns
t
h(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high 7 ns
t
su(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_SMCLK high 7 ns
t
h(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high 2 ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NOE
FSMC_D[15:0]
D1 D2
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 1
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKH-NExH)
t
d(CLKL-AV)
t
d(CLKH-AIV)
t
d(CLKL-NOEL)
t
d(CLKH-NOEH)
t
su(DV-CLKH)
t
h(CLKH-DV)
t
su(DV-CLKH)
t
h(CLKH-DV)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14894d
FSMC_NADV
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)