Datasheet

STM32F101xF, STM32F101xG Electrical characteristics
Doc ID 17143 Rev 2 65/108
Figure 26. Synchronous multiplexed PSRAM write timings
FSMC_CLK
FSMC_NEx
FSMC_NADV
FSMC_A[25:16]
FSMC_NWE
FSMC_AD[15:0]
AD[15:0] D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 1
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKH-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-AV)
t
d(CLKL-NADVH)
t
d(CLKH-AIV)
t
d(CLKH-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-NBLH)
t
d(CLKL-ADV)
t
d(CLKL-ADIV)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14992d
t
d(CLKL-Data)
FSMC_NBL