Datasheet

STM32F101xF, STM32F101xG Description
Doc ID 17143 Rev 2 13/108
Figure 2. Clock tree
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
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INTERFACE