Datasheet

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Preliminary data

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

November 2010 Doc ID 17143 Rev 2 1/108

STM32F101xF

STM32F101xG

XL-density access line, ARM-based 32-bit MCU with 768 KB

to 1 MB Flash, 15 timers, 1 ADC and 10 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU with MPU

– 36 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

performance

– Single-cycle multiplication and hardware

division

■ Memories

– 768 Kbytes to 1 Mbyte of Flash memory

(dual bank with read-while-write capability)

– 80 Kbytes of SRAM

– Flexible static memory controller with 4

Chip Select. Supports Compact Flash,

SRAM, PSRAM, NOR and NAND

memories

– LCD parallel interface, 8080/6800 modes

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

capability

– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

■ 1 x 12-bit, 1 µs A/D converters (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Temperature sensor

■ 2 × 12-bit D/A converters

■ DMA

– 12-channel DMA controller

– Peripherals supported: timers, ADC, DAC,

SPIs, I

Cs and USARTs

■ Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors and almost all

5 V-tolerant

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

– Cortex-M3 Embedded Trace Macrocell™

■ Up to 15 timers

– Up to ten 16-bit timers, with up to 4

IC/OC/PWM or pulse counters

– 2 × watchdog timers (Independent and

Window)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

■ Up to 10 communication interfaces

– Up to 2 x I

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 3 SPIs (18 Mbit/s)

■ CRC calculation unit, 96-bit unique ID

■ ECOPACK

packages

Table 1. Device summary

Reference Part number

STM32F101xF

STM32F101RF STM32F101VF

STM32F101ZF

STM32F101xG

STM32F101RG STM32F101VG

STM32F101ZG

LQFP144

20 × 2

0 mm

LQFP64

× 10 mm

LQFP100

× 14 mm

www.st.com

Summary of content (108 pages)

PAGE 1
STM32F101xF STM32F101xG XL-density access line, ARM-based 32-bit MCU with 768 KB to 1 MB Flash, 15 timers, 1 ADC and 10 communication interfaces Preliminary data Features ■ ■ ■ ■ ■ Core: ARM 32-bit Cortex™-M3 CPU with MPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.
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STM32F101xF, STM32F101xG 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview . . . . . . . . . . . . . .
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STM32F101xF, STM32F101xG 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 6 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.3 Typical curves . . . . . . . . . . . . . . . .
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STM32F101xF, STM32F101xG 6.2.2 Evaluating the maximum junction temperature for an application . . . . 105 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F101xF, STM32F101xG Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49.
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STM32F101xF, STM32F101xG Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. 6/108 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . .
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STM32F101xF, STM32F101xG List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40.
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List of figures Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. 8/108 STM32F101xF, STM32F101xG 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F101xF, STM32F101xG 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F101xF and STM32F101xG XL-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2: Full compatibility throughout the family. The XL-density STM32F101xx datasheet should be read in conjunction with the STM32F10xxx reference manual.
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Description 2 STM32F101xF, STM32F101xG Description The STM32F101xF and STM32F101xG access line family incorporates the highperformance ARM® Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM of 80 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
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STM32F101xF, STM32F101xG 2.1 Description Device overview The STM32F101xx XL-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. ● Figure 1 shows the general block diagram of the device family. Table 2.
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Description STM32F101xF, STM32F101xG TPIU ETM Trace controller Pbus SW/JTAG Trace/trig Ibus MPU Cortex-M3 CPU Fmax: 36 MHz Dbus System NVIC @VDD Flash obl interface NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF Flash 512 Kbyte 64 bit Flash obl interface TRACECLK TRACED[0:3] as AS STM32F101xF and STM32F101xG access line block diagram Bus matrix Figure 1.
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STM32F101xF, STM32F101xG Figure 2. Description Clock tree &,)4&#,+ -(Z (3) 2# (3) &3-##,+ 0ERIPHERAL CLOCK ENABLE -(Z MAX 0,,32# 37 0,,-5, (3) X X X X 0,, 393#,+ !(" 0RESCALER -(Z MAX 0,,#,+ !0" 0RESCALER -(Z MAX 0#,+ TO !0" PERIPHERALS 0ERIPHERAL #LOCK %NABLE !0" 0RESCALER 0,,8402% -(Z (3% /3# TO #ORTEX 3YSTEM TIMER &#,+ #ORTEX FREE RUNNING CLOCK 4)- )F !0" PRESCALER X ELSE X #33 /3#?).
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Description 2.2 STM32F101xF, STM32F101xG Full compatibility throughout the family The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible.
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STM32F101xF, STM32F101xG Description 2.3 Overview 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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Description 2.3.5 STM32F101xF, STM32F101xG Embedded SRAM 80 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.6 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F101xF and STM32F101xG access line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: 2.3.
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STM32F101xF, STM32F101xG 2.3.10 Description Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled.
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Description 2.3.14 STM32F101xF, STM32F101xG Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● MR is used in the nominal regulation mode (Run) ● LPR is used in the Stop modes. ● Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset.
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STM32F101xF, STM32F101xG 2.3.17 Description RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.
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Description STM32F101xF, STM32F101xG one-pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.
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STM32F101xF, STM32F101xG 2.3.19 Description I²C bus Up to two I²C bus interfaces can operate in multi-master and slave modes. They support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.3.
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Description STM32F101xF, STM32F101xG The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.24 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.
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STM32F101xF, STM32F101xG Pinouts and pin descriptions Pinouts and pin descriptions Figure 3.
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Pinouts and pin descriptions STM32F101xF and STM32F101xG LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4.
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STM32F101xF, STM32F101xG STM32F101xF and STM32F101xG LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 5.
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Pinouts and pin descriptions STM32F101xF and STM32F101xG pin definitions (continued) Alternate functions(4) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins I / O level(2) Table 5.
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STM32F101xF, STM32F101xG STM32F101xF and STM32F101xG pin definitions (continued) Pin name Type(1) LQFP100 LQFP64 LQFP144 Pins I / O level(2) Table 5.
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Pinouts and pin descriptions STM32F101xF and STM32F101xG pin definitions (continued) 74 34 52 Pin name PB13 Type(1) LQFP100 LQFP64 LQFP144 Pins I / O level(2) Table 5.
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STM32F101xF, STM32F101xG STM32F101xF and STM32F101xG pin definitions (continued) Pin name Type(1) LQFP100 LQFP64 LQFP144 Pins I / O level(2) Table 5.
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Pinouts and pin descriptions STM32F101xF and STM32F101xG pin definitions (continued) Pin name Type(1) LQFP100 LQFP64 LQFP144 Pins Alternate functions(4) I / O level(2) Table 5.
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STM32F101xF, STM32F101xG Table 6.
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Pinouts and pin descriptions Table 6.
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STM32F101xF, STM32F101xG 4 Memory mapping Memory mapping The memory map is shown in Figure 6. Figure 6.
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Electrical characteristics STM32F101xF, STM32F101xG 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 35
STM32F101xF, STM32F101xG 5.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8. Figure 7. Pin loading conditions Figure 8. Pin input voltage STM32F101 PIN STM32F101 PIN C=50pF VIN ai14123 5.1.6 ai14124 Power supply scheme Figure 9. Power supply scheme 6"!4 "ACKUP CIRCUITRY /3# + 24# 7AKE UP LOGIC "ACKUP REGISTERS /54 '0 ) /S ).
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Electrical characteristics 5.1.7 STM32F101xF, STM32F101xG Current consumption measurement Figure 10. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device.
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STM32F101xF, STM32F101xG Table 8. Electrical characteristics Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F101xF, STM32F101xG 5.3 Operating conditions 5.3.1 General operating conditions Table 10. Symbol General operating conditions Parameter Conditions Min Max fHCLK Internal AHB clock frequency 0 36 fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 36 Standard operating voltage 2 3.6 2 3.
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STM32F101xF, STM32F101xG . Table 12. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst Electrical characteristics (2) VPOR/PDR VPDRhyst (2) Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.
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Electrical characteristics 5.3.4 STM32F101xF, STM32F101xG Embedded reference voltage The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 13.
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STM32F101xF, STM32F101xG Table 14. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK Unit TA = 85 °C External clock (2), all peripherals enabled IDD Supply current in Run mode 36 MHz 41 24 MHz 29 16 MHz 22 8 MHz 12.5 36 MHz 24 24 MHz 17.5 16 MHz 14 8 MHz 8.5 mA External clock (2), all peripherals disabled 1. Based on characterization, not tested in production. 2.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 35 30 8 MHz 16 MHz Consumption (mA) 25 24 MHz 36 MHz 20 15 10 5 0 -45 25 70 85 Temperature (°C) Figure 12. Typical current consumption in Run mode versus frequency (at 3.
PAGE 43
STM32F101xF, STM32F101xG Table 16. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions fHCLK Unit TA = 85 °C External clock(2) all peripherals enabled IDD Supply current in Sleep mode 36 MHz 27.5 24 MHz 20 16 MHz 15 8 MHz 9 36 MHz 6.9 24 MHz 5.9 16 MHz 5.4 8 MHz 4.7 mA External clock(2), all peripherals disabled 1.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 13. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values 2.5 Consumption (µA) 2 1.8 V 1.5 2V 2.4 V 3.3 V 1 3.6 V 0.5 0 –45 25 85 105 Temperature (°C) ai17337 Figure 14. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values 300 Consumption (µA) 250 200 150 100 2.4V 2.7V 3.0V 3.3V 3.
PAGE 45
STM32F101xF, STM32F101xG Electrical characteristics Figure 15. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values 300 Consumption (µA) 250 200 150 100 2.4V 2.7V 3.0V 3.3V 3.6V 50 0 -45 25 70 85 Temperature (°C) Figure 16. Typical current consumption in Standby mode versus temperature at different VDD values 3.5 3 Consumption (µA) 2.5 2 1.5 1 2.4V 2.7V 3.0V 3.3V 3.6V 0.
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Electrical characteristics STM32F101xF, STM32F101xG Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except if it is explicitly mentioned ● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) ● Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) ● When the periph
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STM32F101xF, STM32F101xG Table 19. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions (3) External clock Supply current in Sleep mode IDD fHCLK Typ(1) All peripherals All peripherals enabled(2) disabled 36 MHz 17.7 4 24 MHz 12.2 3.1 16 MHz 8.4 2.3 8 MHz 4.6 1.5 4 MHz 3 1.3 2 MHz 2.15 1.25 1 MHz 1.7 1.2 500 kHz 1.5 1.15 125 kHz 1.35 1.15 36 MHz 17 3.35 24 MHz 11.6 2.3 16 MHz 7.
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Electrical characteristics Table 20. STM32F101xF, STM32F101xG Peripheral current consumption Peripheral APB1 TIM2 0.8 TIM3 0.8 TIM4 0.8 TIM5 0.75 TIM6 0.3 TIM7 0.3 TIM12 0.5 TIM13 0.4 TIM14 0.4 SPI2 0.3 SPI3 0.3 USART2 0.35 USART3 0.35 USART4 0.35 USART5 0.35 I2C1 0.3 I2C2 0.3 CAN 0.45 DAC 48/108 Typical consumption at 25 °C(1) (2) 1.
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STM32F101xF, STM32F101xG Table 20. Electrical characteristics Peripheral current consumption (continued) Peripheral APB2 Typical consumption at 25 °C(1) GPIOA 0.35 GPIOB 0.4 GPIOC 0.4 GPIOD 0.4 GPIOE 0.4 GPIOF 0.4 GPIOG 0.4 TIM1 1 TIM8 1 TIM9 0.5 TIM10 0.4 TIM11 0.4 (3) 1.4 ADC2(3) 1.4 (3) 1.4 ADC1 ADC3 SPI1 0.3 USART1 0.6 Unit mA 1. fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2.
PAGE 50
Electrical characteristics Table 21. STM32F101xF, STM32F101xG High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 8 25 MHz fHSE_ext User external clock source frequency(1) 1 VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.
PAGE 51
STM32F101xF, STM32F101xG Electrical characteristics Figure 17. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC _IN IL STM32F10xxx ai14127b Figure 18.
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Electrical characteristics STM32F101xF, STM32F101xG High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23.
PAGE 53
STM32F101xF, STM32F101xG Electrical characteristics Figure 19. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF Bias controlled gain STM32F10xxx OSC_OU T ai14128b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator.
PAGE 54
Electrical characteristics STM32F101xF, STM32F101xG Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
PAGE 55
STM32F101xF, STM32F101xG Electrical characteristics 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Low-speed internal (LSI) RC oscillator LSI oscillator characteristics (1) Table 26.
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Electrical characteristics 5.3.8 STM32F101xF, STM32F101xG PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28. PLL characteristics Value Symbol Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.
PAGE 57
STM32F101xF, STM32F101xG Table 30. Electrical characteristics Flash memory endurance and data retention Value Symbol NEND Parameter Endurance Conditions TA = –40 °C to 85 °C (2) tRET Data retention Min(1) 10 TA = 85 °C, 1 kcycle 30 TA = 55 °C, 10 kcycle(2) 20 Unit kcycles Years 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.
PAGE 58
Electrical characteristics STM32F101xF, STM32F101xG Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &3-#?.% T V ./%?.% T W ./% T H .%?./% &3-#?./% &3-#?.7% TV !?.% &3-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &3-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &3-#?$; = T V .!$6?.% TW .!$6 &3-#?.!$6 -3 6 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31.
PAGE 59
STM32F101xF, STM32F101xG Electrical characteristics Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Table 31. Symbol Parameter Min Max Unit tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 5 ns tw(NADV) FSMC_NADV low time THCLK + 1.5 ns 1. CL = 15 pF. 2. Preliminary values. Figure 22.
PAGE 60
Electrical characteristics STM32F101xF, STM32F101xG Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Table 32. Symbol Parameter Min Max Unit tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 5.5 ns tw(NADV) FSMC_NADV low time THCLK + 1.5 ns 1. CL = 15 pF. 2. Preliminary values. Figure 23.
PAGE 61
STM32F101xF, STM32F101xG Table 33.
PAGE 62
Electrical characteristics STM32F101xF, STM32F101xG Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 34.
PAGE 63
STM32F101xF, STM32F101xG Electrical characteristics Synchronous waveforms and timings Figure 25 through Figure 28 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings.
PAGE 64
Electrical characteristics Table 35. STM32F101xF, STM32F101xG Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x = 16...
PAGE 65
STM32F101xF, STM32F101xG Electrical characteristics Figure 26.
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Electrical characteristics Table 36. STM32F101xF, STM32F101xG Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x = 16...
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STM32F101xF, STM32F101xG Electrical characteristics Figure 27.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 28. Synchronous non-multiplexed PSRAM write timings BUSTURN = 0 tw(CLK) tw(CLK) FSMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 1 FSMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FSMC_NADV td(CLKL-AV) td(CLKH-AIV) FSMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH) FSMC_NWE td(CLKL-Data) FSMC_D[15:0] td(CLKL-Data) D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKL-NBLH) th(CLKH-NWAITV) FSMC_NBL ai14993e Table 38.
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STM32F101xF, STM32F101xG Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 29 through Figure 34 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime = 0x00; ● ATT.FSMC_SetupTime = 0x04; ● ATT.FSMC_WaitSetupTime = 0x07; ● ATT.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 30.
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STM32F101xF, STM32F101xG Electrical characteristics Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded).
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Electrical characteristics STM32F101xF, STM32F101xG Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 33.
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STM32F101xF, STM32F101xG Electrical characteristics Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 tv(NCEx-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) tw(NIOWR) FSMC_NIOWR ATTxHIZ =1 tv(NIOWR-D) th(NIOWR-D) FSMC_D[15:0] ai14900b Table 39.
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Electrical characteristics Table 39.
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STM32F101xF, STM32F101xG Electrical characteristics Figure 35. NAND controller waveforms for read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) th(NOE-ALE) FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14901b Figure 36. NAND controller waveforms for write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) th(NWE-ALE) FSMC_NWE FSMC_NOE (NRE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14902b Figure 37.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 38. NAND controller waveforms for common memory write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FSMC_NWE FSMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14913b Table 40. Switching characteristics for NAND Flash read and write cycles(1) Symbol td(D-NWE)(2) Parameter Min Unit FSMC_D[15:0] valid before FSMC_NWE high 6THCLK + 12 ns FSMC_NOE low width 4THCLK – 1.5 4THCLK + 1.
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STM32F101xF, STM32F101xG 5.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32F101xF, STM32F101xG Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 42. EMI characteristics Symbol Parameter SEMI 5.3.12 Peak level Conditions Max vs. [fHSE/fHCLK] Monitored frequency band Unit 8/36 MHz 0.
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STM32F101xF, STM32F101xG 5.3.13 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
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Electrical characteristics 5.3.14 STM32F101xF, STM32F101xG I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 46. Symbol VIL VIH Vhys Ilkg I/O static characteristics Parameter Conditions Min Typ Max Unit Standard IO input low level voltage –0.3 0.28*(VDD-2 V)+0.
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STM32F101xF, STM32F101xG Electrical characteristics Figure 39. Standard I/O input characteristics - CMOS port 6)( 6), 6 6 $$ ENT 6 )( #-/3 7)(MIN 7),MAX 6 6 )( $$ QUIREM NDARD RE 6 6), $$ 6 $$ IREMENT 6 ), RD REQU #-/3 STANDA )NPUT RANGE NOT GUARANTEED STA 6$$ 6 AI B Figure 40.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 41. 5 V tolerant I/O input characteristics - CMOS port 6)( 6), 6 6 $$ TS 6 )( UIREMEN ARD REQ 3 STAND #-/ 6 ), 6 $$ T 6 ), 6 $$ REQUIRMEN /3 STANDARD #- 6 )( 6 $$ )NPUT RANGE NOT GUARANTEED 6$$ 6 6$$ AI B Figure 42.
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STM32F101xF, STM32F101xG Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 47.
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Electrical characteristics STM32F101xF, STM32F101xG Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 43 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 48.
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STM32F101xF, STM32F101xG Electrical characteristics Figure 43. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46).
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Electrical characteristics 5.3.16 STM32F101xF, STM32F101xG TIM timer characteristics The parameters given in Table 50 are guaranteed by design. Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max 1 tTIMxCLK 27.
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STM32F101xF, STM32F101xG Table 51. Electrical characteristics I2C characteristics Standard mode I2C(1) Fast mode I2C(1)(2) Symbol Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 (3) 0(4) 900(3) 20+0.1Cb 300 µs th(SDA) SDA data hold time tr(SDA) tr(SCL) SDA and SCL rise time 1000 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 45. I2C bus AC waveforms and measurement circuit(1) 6$$ 6$$ K K 34- & XXX 3$! )£# BUS 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU 34! 3$! TF 3$! TR 3$! TH 34! TSU 3$! TW 3#,, 3#, TW 3#,( TR 3#, TSU 34/ 34! 3 4/0 TH 3$! TSU 34/ TF 3#, AI C 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 52. SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V)(1)(2) fSCL I2C_CCR value (kHz) RP = 4.
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STM32F101xF, STM32F101xG Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 53Table 54 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 53.
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Electrical characteristics Table 54.
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STM32F101xF, STM32F101xG Electrical characteristics Figure 46. SPI timing diagram - slave mode and CPHA=0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 47.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 48. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 5.3.
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STM32F101xF, STM32F101xG Table 55. Symbol Electrical characteristics ADC characteristics Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V VREF+ Positive reference voltage 2.4 VDDA V IVREF Current on the VREF input pin 220(1) µA fADC ADC clock frequency 0.6 14 MHz fS(2) Sampling rate 0.
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Electrical characteristics STM32F101xF, STM32F101xG The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 56. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (k) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 57.
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STM32F101xF, STM32F101xG ADC accuracy(1) (2)(3) Table 58. Symbol ET Electrical characteristics Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 28 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
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Electrical characteristics STM32F101xF, STM32F101xG Figure 50. Typical connection diagram using the ADC STM32F10xxx VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VT 0.6 V VAIN Cparasitic IL±1 µA 12-bit converter CADC(1) ai14139d 1. Refer to Table 55 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
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STM32F101xF, STM32F101xG Electrical characteristics Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F10xxx VREF+/VDDA 1 µF // 10 nF VREF–/VSSA ai14381b 1. VREF+ and VREF- inputs are available only on 100-pin packages. 5.3.19 DAC electrical specifications Table 59. DAC characteristics Symbol Parameter Min Max(1) Typ Unit Comments VDDA Analog supply voltage 2.4 3.6 V VREF+ Reference supply voltage 2.4 3.
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Electrical characteristics Table 59.
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STM32F101xF, STM32F101xG Electrical characteristics Figure 53. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.
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Package characteristics STM32F101xF, STM32F101xG 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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STM32F101xF, STM32F101xG Package characteristics Figure 54. LQFP144, 20 x 20 mm, 144-pin thin quad flat package outline(1) Figure 55. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.25 mm gage plane C D k 108 109 1.35 73 72 0.35 D1 A1 D3 0.5 L 73 108 L1 17.85 19.9 72 109 144 E1 22.6 37 E 1 E3 36 19.9 22.6 ai149 144 Pin 1 identification 37 36 1 e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 61.
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Package characteristics STM32F101xF, STM32F101xG Figure 56. LQFP100 – 14 x 14 mm, 100-pin low-profile Figure 57. Recommended footprint(1)(2) quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE k 75 51 D L D1 76 L1 D3 51 75 50 0.5 C 76 0.3 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 26 Pin 1 1 identification 25 12.3 25 C ccc 16.7 ai14906b e A1 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 62.
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STM32F101xF, STM32F101xG Package characteristics Figure 58. LQFP64 – 10 x 10 mm, 64 pin low-profile quad Figure 59. Recommended flat package outline(1) footprint(1)(2) D 48 ccc C D1 33 48 33 A A2 D3 0.3 49 32 0.5 32 49 12.7 b 10.3 L1 10.3 E3 E1 E 64 17 1.2 L A1 K 1 16 7.8 64 17 Pin 1 identification 12.7 16 1 c ai14909 5W_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 63.
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Package characteristics 6.2 STM32F101xF, STM32F101xG Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 38.
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STM32F101xF, STM32F101xG Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 65: STM32F101xF and STM32F101xG ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C).
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Part numbering 7 STM32F101xF, STM32F101xG Part numbering Table 65. STM32F101xF and STM32F101xG ordering information scheme Example: STM32 F 101 R F T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 101 = access line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size F = 768 Kbytes of Flash memory G = 1 Mbyte of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C.
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STM32F101xF, STM32F101xG 8 Revision history Revision history Table 66. Document revision history Date Revision 27-Oct-2009 1 Initial release. 2 LQFP64 package mechanical data updated: see Figure 58: LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline and Table 63: LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data. Internal code removed from Table 65: STM32F101xF and STM32F101xG ordering information scheme.
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STM32F101xF, STM32F101xG Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.