Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 36 MHz I/O number 80

This is information on a product in full production.

August 2013 DocID13586 Rev 16 1/90

STM32F101x8

STM32F101xB

Medium-density access line, ARM-based 32-bit MCU with 64 or

128 KB Flash, 6 timers, ADC and 7 communication interfaces

Datasheet - production data

Features

 Core: ARM 32-bit Cortex™-M3

CPU

– 36 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

 Memories

– 64 to 128 Kbytes of Flash memory

– 10 to 16 Kbytes of SRAM

 Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

 Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

 Debug mode

– Serial wire debug (SWD) and JTAG

interfaces

 DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

Cs and USARTs

 1 × 12-bit, 1 µs A/D converter (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Temperature sensor

 Up to 80 fast I/O ports

– 26/37/51/80 I/Os, all mappable on 16

external interrupt vectors and almost all

5 V-tolerant

 Six timers

– Three 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 2 watchdog timers (Independent and

Window)

– SysTick timer: 24-bit downcounter

 Up to 7 communication interfaces

– Up to 2 x I

C interfaces (SMBus/PMBus)

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 2 SPIs (18 Mbit/s)

 CRC calculation unit, 96-bit unique ID

 ECOPACK

packages

Table 1. Device summary

Reference Part number

STM32F101x8

STM32F101C8,

STM32F101R8

STM32F101V8,

STM32F101T8

STM32F101xB

STM32F101RB,

STM32F101VB,

STM32F101CB

STM32F101TB

LQFP48

7 x 7 mm

LQFP100

14 x 14 mm

LQFP64

10 x 10 mm

VFQFPN36

6 × 6 mm

UFQFPN48

7 × 7 mm

www.st.com

Summary of content (90 pages)

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STM32F101x8 STM32F101xB Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Datasheet - production data Features  Core: ARM 32-bit Cortex™-M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 to 128 Kbytes of Flash memory – 10 to 16 Kbytes of SRAM LQFP48 7 x 7 mm  Clock, reset and supply management – 2.0 to 3.
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Contents STM32F101x8, STM32F101xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2/90 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.
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STM32F101x8, STM32F101xB Contents 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 6 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.2 Typical values . . . . . . . . . . . . . . .
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Contents STM32F101x8, STM32F101xB 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F101x8, STM32F101xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . .
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List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. 6/90 STM32F101x8, STM32F101xB ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F101x8, STM32F101xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. 8/90 STM32F101x8, STM32F101xB LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 78 LQFP64 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F101x8, STM32F101xB 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F101x8 and STM32F101xB medium-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F101xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual.
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Description 2 STM32F101x8, STM32F101xB Description The STM32F101xB and STM32F101x8 medium-density access line family incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 16 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses.
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STM32F101x8, STM32F101xB Device overview Figure 1 shows the general block diagram of the device family. Table 2. Device features and peripheral counts (STM32F101xx medium-density access line) Peripheral STM32F101Tx STM32F101Cx STM32F101Rx STM32F101Vx 64 128 64 128 64 128 64 128 SRAM - Kbytes 10 16 10 16 10 16 10 16 Timers Flash - Kbytes Communication 2.
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Description STM32F101x8, STM32F101xB Figure 1.
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STM32F101x8, STM32F101xB Description Figure 2. Clock tree FLITFCLK to Flash programming interface 8 MHz HSI RC HSI /2 36 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK PLLCLK 36 MHz max AHB Prescaler /1, 2..
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Description 2.2 STM32F101x8, STM32F101xB Full compatibility throughout the family The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are referred to as high-density devices.
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STM32F101x8, STM32F101xB Description 2.3 Overview 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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Description 2.3.6 STM32F101x8, STM32F101xB External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period.
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STM32F101x8, STM32F101xB Description higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 10: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.11 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down.
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Description STM32F101x8, STM32F101xB Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC. 2.3.
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STM32F101x8, STM32F101xB Description capture, output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.
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Description STM32F101x8, STM32F101xB An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. 2.3.24 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V.
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STM32F101x8, STM32F101xB Pinouts and pin description 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 3.
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Pinouts and pin description STM32F101x8, STM32F101xB VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 4.
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STM32F101x8, STM32F101xB Pinouts and pin description VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 6.
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Pinouts and pin description STM32F101x8, STM32F101xB Table 4.
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STM32F101x8, STM32F101xB Pinouts and pin description Table 4.
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Pinouts and pin description STM32F101x8, STM32F101xB Table 4.
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STM32F101x8, STM32F101xB Pinouts and pin description Table 4.
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Pinouts and pin description STM32F101x8, STM32F101xB Table 4. Medium-density STM32F101xx pin definitions (continued) Alternate functions(3)(4) LQFP100 VFQFPN36 I / O level(2) LQFP64 Main function(3) (after reset) LQFP48/ UFQFPN48 Type(1) Pins 47 63 99 36 VSS_3 S VSS_3 48 64 100 1 VDD_3 S VDD_3 Pin name Default Remap 1. I = input, O = output, S = supply, HiZ= high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device.
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STM32F101x8, STM32F101xB 4 Memory mapping Memory mapping The memory map is shown in Figure 8. Figure 8.
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Electrical characteristics STM32F101x8, STM32F101xB 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F101x8, STM32F101xB Electrical characteristics Figure 9. Pin loading conditions Figure 10. Pin input voltage STM32F10xxx pin STM32F10xxx pin C = 50 pF VIN ai14124b ai14123b 5.1.6 Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 × 100 nF + 1 × 4.
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Electrical characteristics 5.1.7 STM32F101x8, STM32F101xB Current consumption measurement Figure 12. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics, Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent damage to the device.
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STM32F101x8, STM32F101xB Electrical characteristics Table 6. Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F101x8, STM32F101xB Table 8. General operating conditions (continued) Symbol Parameter Conditions Min Max –0.3 VDD + 0.3 2 V < VDD  3.6 V –0.3 5.5 VDD = 2 V –0.3 5.2 0 5.
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STM32F101x8, STM32F101xB . Electrical characteristics Table 10. Embedded reset and power control block characteristics Symbol VPVD Parameter Conditions Programmable voltage detector level selection VPVDhyst(2) PVD hysteresis VPOR/PDR Power on/power down reset threshold VPDRhyst(2) PDR hysteresis Min Typ Max PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 PLS[2:0]=000 (falling edge) 2 2.08 2.16 PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 PLS[2:0]=001 (falling edge) 2.09 2.18 2.
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Electrical characteristics 5.3.4 STM32F101x8, STM32F101xB Embedded reference voltage The parameters given in Table 11 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 11.
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STM32F101x8, STM32F101xB Electrical characteristics Table 12. Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions External clock (2), all peripherals enabled IDD Supply current in Run mode External clock (4), all peripherals Disabled fHCLK Unit TA = 85 °C 36 MHz 28.6 24 MHz 19.9 16 MHz 14.7 8 MHz 8.6 36 MHz 19.8 24 MHz 13.9 16 MHz 10.7 8 MHz 6.8 mA 1. Based on characterization, not tested in production. 2.
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Electrical characteristics STM32F101x8, STM32F101xB Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 25 Consumption (mA) 20 15 36MHz 16MHz 8MHz 10 5 0 -40 0 25 70 85 Temperature (°C) Figure 14. Typical current consumption in Run mode versus frequency (at 3.
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STM32F101x8, STM32F101xB Electrical characteristics Table 14. Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions fHCLK External clock(2) all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled Unit TA = 85 °C 36 MHz 15.5 24 MHz 11.5 16 MHz 8.5 8 MHz 5.5 36 MHz 5 24 MHz 4.5 16 MHz 4 8 MHz 3 mA 1.
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Electrical characteristics STM32F101x8, STM32F101xB Figure 15. Typical current consumption on VBAT with RTC on versus temperature at different VBAT values Consumption ( µA ) 2.5 2 2V 1.5 2.4 V 1 3V 0.5 3.6 V 0 –40 °C 25 °C 70 °C 85 °C 105 °C Temperature (°C) ai17351 Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V 140 Consumption (µA) 120 100 80 3.3 V 3.
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STM32F101x8, STM32F101xB Electrical characteristics Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 100 90 Consumption (µA) 80 70 60 3.3 V 50 3.6 V 40 30 20 10 0 –45 °C 25 °C 85 °C Temperature (°C) Figure 18. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 3 Consumption (µA) 2.5 2 3.3 V 1.5 3.6 V 1 0.
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Electrical characteristics STM32F101x8, STM32F101xB Typical current consumption The MCU is placed under the following conditions:  All I/O pins are in input mode with a static value at VDD or VSS (no load)  All peripherals are disabled except if it is explicitly mentioned  The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz)  Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)  When the periph
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STM32F101x8, STM32F101xB Electrical characteristics Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Sleep mode Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK Typ(1) All peripherals All peripherals enabled(2) disabled 36 MHz 7.6 3.1 24 MHz 5.3 2.3 16 MHz 3.8 1.8 8 MHz 2.1 1.2 4 MHz 1.6 1.1 2 MHz 1.3 1 1 MHz 1.11 0.
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Electrical characteristics STM32F101x8, STM32F101xB On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 18.
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STM32F101x8, STM32F101xB Electrical characteristics Table 19. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 25 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.
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Electrical characteristics STM32F101x8, STM32F101xB Figure 19. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE External clock source fHSE_ext OSC _IN IL STM32F10xxx ai14127b Figure 20.
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STM32F101x8, STM32F101xB Electrical characteristics Table 21. HSE 4-16 MHz oscillator characteristics(1)(2) Symbol fOSC_IN Parameter Conditions Min Typ Max Unit 4 8 16 MHz Oscillator frequency RF Feedback resistor 200 k C Recommended load capacitance versus equivalent serial RS = 30 resistance of the crystal (RS)(3) 30 pF i2 HSE driving current VDD = 3.
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Electrical characteristics STM32F101x8, STM32F101xB time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2) Symbol Parameter Conditions Min Typ Max RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS) RS = 30 K 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS 1.
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STM32F101x8, STM32F101xB Electrical characteristics Figure 22. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 KH z resonator RF Bias controlled gain STM32F10xxx OSC32_OU T CL2 ai14129b 5.3.7 Internal clock source characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. High-speed internal (HSI) RC oscillator Table 23.
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Electrical characteristics STM32F101x8, STM32F101xB Low-speed internal (LSI) RC oscillator Table 24. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI)(3) IDD(LSI) (3) Parameter Frequency Min Typ Max Unit 30 40 60 kHz 85 µs 1.2 µA LSI oscillator startup time LSI oscillator power consumption 0.65 1. VDD = 3 V, TA = –40 to 85 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
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STM32F101x8, STM32F101xB Electrical characteristics Table 26. PLL characteristics Value Symbol Parameter Min(1) Unit Max(1) Typ tLOCK PLL lock time 200 µs Jitter Cycle-to-cycle jitter 300 ps 1. Based on device characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.
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Electrical characteristics STM32F101x8, STM32F101xB Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:  Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
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STM32F101x8, STM32F101xB Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC61967-2 standard which specifies the test board and the pin loading. Table 30. EMI characteristics Symbol Parameter SEMI 5.3.11 Peak level Conditions Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/36 MHz 0.
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Electrical characteristics STM32F101x8, STM32F101xB Table 32. Electrical sensitivities Symbol LU 5.3.12 Parameter Static latch-up class Conditions Class TA +85 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation.
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STM32F101x8, STM32F101xB 5.3.13 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 34. I/O static characteristics Symbol VIL VIH Parameter Min Typ Max Standard IO input low level voltage - - 0.28*(VDD-2 V)+0.8 V(1) IO FT(3) input low level voltage - - 0.32*(VDD-2 V)+0.
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Electrical characteristics STM32F101x8, STM32F101xB All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and in Figure 25 and Figure 26 for 5 V tolerant I/Os. Figure 23. Standard I/O input characteristics - CMOS port Area not determined VIH/VIL (V) =0.
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STM32F101x8, STM32F101xB Electrical characteristics Figure 25. 5 V tolerant I/O input characteristics - CMOS port Area not determined VIH/VIL (V) 5V D V =0.6 D irements IH CMOS in Tested on 1.42 1.07 1.295 0.975 1 0.75 -2)+1 V IH=0.42(V DD simulations design on d se Ba 1.67 -2)+0.75 1.55 1 V IL=0.32(V DD ns gn simulatio si 1.16 de on d Base 5V ent V IL =0.3 DD dard requirm producti 1.3 0.7 requ standard CMOS stan tion ed in produc Test 2 3 2.7 3.3 VDD (V) 3.6 VDD ai17279c Figure 26.
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Electrical characteristics STM32F101x8, STM32F101xB Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
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STM32F101x8, STM32F101xB Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 27 and Table 36, respectively. Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 36.
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Electrical characteristics STM32F101x8, STM32F101xB Figure 27. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON 50pF tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 34).
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STM32F101x8, STM32F101xB Electrical characteristics Figure 28. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal reset Filter 0.1 µF STM32F10x ai14132d 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 37. Otherwise the reset will not be taken into account by the device.
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Electrical characteristics 5.3.15 STM32F101x8, STM32F101xB TIM timer characteristics The parameters given in Table 38 are guaranteed by design. Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 38.
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STM32F101x8, STM32F101xB Electrical characteristics Table 39. I2C characteristics Standard mode I2C(1) Fast mode I2C(1)(2) Symbol Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 0 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20+0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.
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Electrical characteristics STM32F101x8, STM32F101xB Figure 29. I2C bus AC waveforms and measurement circuit(1) VDD_I2C VDD_I2C Rp Rp STM32F10x Rs SDA I²C bus Rs SCL Start repeated Start Start tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) tw(SCLL) th(SDA) tsu(STO:STA) Stop SCL tw(SCLH) tr(SCL) tsu(STO) tf(SCL) ai14133e 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 2. Rs = Series protection resistors, Rp = Pull-up resistors, VDD_I2C = I2C bus supply. Table 40.
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STM32F101x8, STM32F101xB Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41.
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Electrical characteristics STM32F101x8, STM32F101xB Figure 30. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 31.
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STM32F101x8, STM32F101xB Electrical characteristics Figure 32. SPI timing diagram - master mode(1) High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MS BIN tr(SCK) tf(SCK) BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics 5.3.17 STM32F101x8, STM32F101xB 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 8. Note: It is recommended to perform a calibration after each power-up. Table 42. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.
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STM32F101x8, STM32F101xB Electrical characteristics Equation 1: RAIN max formula: TS R AIN  ------------------------------------------------------------- – R ADC N+2 f ADC  C ADC  ln  2  The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 43. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (k) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.
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Electrical characteristics STM32F101x8, STM32F101xB Table 45. ADC accuracy(1) (2) (3) Symbol Parameter Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 28 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
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STM32F101x8, STM32F101xB Electrical characteristics Figure 34. Typical connection diagram using the ADC STM32F10xxx VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VT 0.6 V VAIN Cparasitic 12-bit converter CADC(1) IL±1 µA ai14139d 1. Refer to Table 42 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
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Electrical characteristics STM32F101x8, STM32F101xB Figure 36. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F10xxx VREF+/VDDA 1 µF // 10 nF VREF–/VSSA ai14381b 1. VREF+ and VREF- inputs are available only on 100-pin packages. 5.3.18 Temperature sensor characteristics Table 46. TS characteristics Symbol TL(1) Parameter Min VSENSE linearity with temperature Typ Max Unit 1 2 °C Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C V25(1) Voltage at 25°C 1.34 1.
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STM32F101x8, STM32F101xB Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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Package characteristics STM32F101x8, STM32F101xB Figure 37. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline Pin 1 indentifier laser marking area D A E E T ddd Seating plane A1 b e Detail Y D Exposed pad area Y D2 1 L 48 C 0.500x45° pin1 corner R 0.125 typ. Detail Z E2 1 48 Z A0B9_ME_V3 1. Drawing is not to scale. 2. There is an exposed die pad on the underside of the QFPN package, this pad is not internally connected to the VSS or VDD power pads. It is recommended to connect it to VSS.
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STM32F101x8, STM32F101xB Package characteristics Table 47. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 38. UFQFPN48 recommended footprint 7.30 6.20 48 37 1 36 5.60 0.20 7.30 5.80 6.20 5.60 0.30 12 25 13 0.55 24 0.50 5.
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Package characteristics STM32F101x8, STM32F101xB Figure 39. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) Figure 40. VFQFPN36 recommended footprint (dimensions in mm)(1)(2) Seating plane C ddd C A2 A 1.00 4.30 27 A1 A3 19 E2 28 18 b 27 19 0.50 4.10 18 28 4.30 4.10 4.80 4.80 e D2 D 36 10 9 1 0.75 0.30 36 10 6.30 ai14870b Pin # 1 ID R = 0.20 1 9 L E ZR_ME 1. Drawing is not to scale. 2.
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STM32F101x8, STM32F101xB Package characteristics Figure 41. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline(1) Figure 42. LQFP100 recommended footprint(1)(2) SEATING PLANE C c A1 A A2 75 51 0.25 mm GAUGE PLANE 76 50 0.5 ccc C L D1 0.3 A1 K D 16.7 L1 14.3 D3 51 75 50 76 b 100 26 E E3 E1 1.2 1 25 12.3 16.7 100 26 PIN 1 1 IDENTIFICATION ai14906 25 e 1L_ME_V5 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 49.
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Package characteristics STM32F101x8, STM32F101xB Figure 43. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline(1) Figure 44. LQFP64 recommended footprint(1)(2) SEATING PLANE 0.25 mm GAUGE PLANE 48 33 c A1 A A2 C 0.3 49 A1 ccc C D 32 0.5 K L D1 12.7 L1 D3 10.3 33 48 32 49 10.3 64 17 1.2 E E1 E3 b 1 16 7.8 64 12.7 17 ai14909 PIN 1 IDENTIFICATION 16 1 e 5W_ME_V3 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 50.
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STM32F101x8, STM32F101xB Package characteristics Figure 45. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package outline(1) Figure 46. LQFP48 recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.50 1.20 0.25 mm Gage plane C 36 D 0.30 25 37 24 D1 k D3 A1 L 25 36 9.70 0.20 7.30 5.80 L1 7.30 24 37 48 13 12 1 1.20 E3 E1 5.80 E 9.70 ai14911b 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 51.
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Package characteristics 6.2 STM32F101x8, STM32F101xB Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 8: General operating conditions on page 33.
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STM32F101x8, STM32F101xB Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 53: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C).
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Ordering information scheme 7 STM32F101x8, STM32F101xB Ordering information scheme Table 53.
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STM32F101x8, STM32F101xB 8 Revision history Revision history Table 54. Document revision history Date Revision 06-Jun-2007 1 First draft. 2 IDD values modified in Table 11: Maximum current consumption in Run and Sleep modes (TA = 85 °C). VBAT range modified in Power supply schemes. VREF+ min value, tSTAB, tlat and fTRIG added to Table 42: ADC characteristics. Table 38: TIMx characteristics modified.
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Revision history STM32F101x8, STM32F101xB Table 54. Document revision history (continued) Date 18-Oct-2007 84/90 Revision Changes 3 VESD(CDM) value added to Table 31: ESD absolute maximum ratings. Note added below Table 10: Embedded reset and power control block characteristics. and below Table 21: HSE 4-16 MHz oscillator characteristics. Note added below Table 35: Output voltage characteristics and VOH parameter description modified.
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STM32F101x8, STM32F101xB Revision history Table 54. Document revision history (continued) Date 22-Nov-2007 Revision Changes 4 Document status promoted from preliminary data to datasheet. Small text changes. STM32F101CB part number corrected in Table 1: Device summary. Number of communication peripherals corrected for STM32F101Tx in Table 2: Device features and peripheral counts (STM32F101xx mediumdensity access line) and Number of GPIOs corrected for LQFP package.
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Revision history STM32F101x8, STM32F101xB Table 54. Document revision history (continued) Date 14-Mar-2008 21-Mar-2008 22-May-2008 86/90 Revision Changes 5 Figure 2: Clock tree on page 13 added. CRC added (see CRC (cyclic redundancy check) calculation unit on page 9 and Figure 8: Memory map on page 29 for address). Maximum TJ value given in Table 7: Thermal characteristics on page 33.
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STM32F101x8, STM32F101xB Revision history Table 54. Document revision history (continued) Date Revision Changes 21-Jul-2008 8 Small text changes. Power supply supervisor on page 16 modified and VDDA added to Table 8: General operating conditions on page 33. Capacitance modified in Figure 11: Power supply scheme on page 31. Table notes revised in Section 5: Electrical characteristics. Maximum value of tRSTTEMPO modified in Table 10: Embedded reset and power control block characteristics on page 35.
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Revision history STM32F101x8, STM32F101xB Table 54. Document revision history (continued) Date 21-Apr-2009 22-Sep-2009 20-May-2010 88/90 Revision Changes 11 I/O information clarified on page 1. Figure 8: Memory map modified. In Table 4: Medium-density STM32F101xx pin definitions: PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column.
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STM32F101x8, STM32F101xB Revision history Table 54. Document revision history (continued) Date 19-Apr-2011 15-May-2013 05-Aug-2013 Revision Changes 14 Updated footnotes below Table 5: Voltage characteristics on page 32 and Table 6: Current characteristics on page 33 Updated tw min in Table 19: High-speed external user clock characteristics on page 45 Updated startup time in Table 22: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 48 Added Section 5.3.
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STM32F101x8, STM32F101xB Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.