Datasheet

Description STM32F101xC, STM32F101xD, STM32F101xE
12/112 Doc ID 14610 Rev 8
Figure 1. STM32F101xC, STM32F101xD and STM32F101xE access line block
diagram
1. T
A
= –40 °C to +85 °C (junction temperature up to 105 °C).
2. AF = alternate function on I/O port pin.
PA[15:0]
EXT.IT
112AF
AHB2
WKUP
F
max
: 36 MHz
V
SS
I2C2
GP DMA1
TIM2
TIM3
XTAL 32kHz
Flash 512 Kbytes
V
DD
Backup interface
TIM4
Bus Matrix
64 bit
RTC
RC 8 MHz
Cortex-M3 CPU
Dbus
obl
Flash interface
USART 2
SPI2
Back up
reg
I2C1
RX, TX, CTS, R T S,
USART 3
RC 40 kHz
Standby
IWDG
@
V
BAT
POR / PDR
@V
DDA
V
BAT
=1.8 V to 3.6 V
CK, as AF
RX, TX, CTS, RTS,
CK, as AF
NVIC
SPI1
interface
@VDDA
PVD
Int
AHB2
APB2
AWU
SPI3
UART4
RX,TX as AF
UART5
RX,TX as AF
TIM5
PLL
@V
DDA
FSMC
DAC_OUT1 as AF
DAC_OUT2 as AF
SRAM
48 KB
GP DMA2
TIM6
TIM7
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[4:1]
NBL[1:0]
NWAIT
NL
as AF
7 channels
5 channels
GPIO port A
GPIO port B
GPIO port C
GPIO port D
GPIO port E
GPIO port F
GPIO port G
USART1
Temp. sensor
12-bit ADC IF
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
ADC_IN[0:15]
@ V
DDA
APB2: Fmax = 24/36 MHz
APB1
Trace
controller
Pbus
Ibus
System
Reset &
Clock
control
PCLK1
PCLK2
HCLK
FCLK
Power
Volt. reg.
3.3 V to 1.8 V
Supply
supervision
@V
DD
POR
Reset
NRST
V
DDA
V
SSA
OSC_IN
OSC_OUT
@V
DD
XTAL OSC
4-16 MHz
OSC32_IN
OSC32_OUT
TAMPER-RTC/
ALARM/SECOND OUT
4 channels as AF
4 channels as AF
4 channels as AF
4 channels as AF
MOSI, MISO
SCK, NSS as AF
MOSI, MISO
SCK, NSS as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
WWDG
ai14693d
APB1: F
max
= 24/36 MHz
TRACECLK
TRACED[0:3]
as AS
SW/JTAG
TPIU
Trace/trig
V
REF+
V
REF–
MOSI, MISO, SCK,
NSS as AF
RX, TX, CTS, RTS
as AF
12bit DAC1
IFIF
IF
12bit DAC 2