Datasheet

Memory mapping STM32F100xC, STM32F100xD, STM32F100xE

32/98 Doc ID 15081 Rev 7

4 Memory mapping

The memory map is shown in Figure 6.

PD7 NE1 NE1 Yes

PG9 NE2 NE2 -

PG10 NE3 NE3 -

PG11 -

PG12 NE4 NE4 -

PG13 A24 A24 -

PG14 A25 A25 -

PB7 NADV NADV Yes

PE0 NBL0 NBL0 Yes

PE1 NBL1 NBL1 Yes

1. Ports F and G are not available in devices delivered in 100-pin packages.

Table 5. FSMC pin definition (continued)

Pins

FSMC

LQFP100

(1)

NOR/PSRAM/SRAM NOR/PSRAM Mux