Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 24 MHz I/O number 80

Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE

30/98 Doc ID 15081 Rev 7

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one

peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC

peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited

amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not

exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to

drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup

registers even after reset (because these registers are not reset by the main reset). For details on how to

manage these IOs, refer to the Battery backup domain and BKP register description sections in the

STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com.

7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,

however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100

and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For

more details, refer to Alternate function I/O and debug configuration section in the STM32F100xx

reference manual.

8. This alternate function can be remapped by software to some other port pins (if available on the used

package). For more details, refer to the Alternate function I/O and debug configuration section in the

STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com.

9. For devices delivered in LQFP64 packages, the FSMC function is not available.

Table 5. FSMC pin definition

Pins

FSMC

LQFP100

(1)

NOR/PSRAM/SRAM NOR/PSRAM Mux

PE2 A23 A23 Yes

PE3 A19 A19 Yes

PE4 A20 A20 Yes

PE5 A21 A21 Yes

PE6 A22 A22 Yes

PF0 A0 -

PF1 A1 -

PF2 A2 -

PF3 A3 -

PF4 A4 -

PF5 A5 -

PF6 -

PF7 -

PF8 -

PF9 -

PF10 -

PF11 -

PF12 A6 -

PF13 A7 -